本論文係以CMOS 製程研製無線方向定位晶片，此系統可辨識方向、量測距離與定位，為了要容易整合成單一晶片，不採用現有可用之通訊技術，而是採用自行設計之無線通訊系統，並使用鎖相迴路技術，可使系統更為精確以提昇穩定性，規格如下： 操作頻率：2.4GHz-2.4835GHz (ISM) 、傳輸距離:10-15 公尺、中頻頻率:320MHz-400MHz、系統操作頻率:350MHz、量測範圍:0.857公尺。
　　依據所訂出的電路規格，以TSMC 0.18μm 1P6M CMOS 製程研擬射頻發射機及製作射頻接收機、鎖相迴路與相位計數器電路，若能繼續整合其他電路實現無線通信晶片於單一晶片，相信對於科學技術將有一定之貢獻。

　In this thesis, the wireless positioning chip is designed and implemented in CMOS
process.This chip can measure the direction, the distance and the location. For the integrated of the system chips, we can use the simple design for the wireless communication system. It contains LNA, VCO, Mixer, PA and PLL. The specification of this system is shown: operating radio frequency is 2.4 GHz~2.4835 GHz, the transmission distance is 10~15m, the intermediate frequency is 320 MHz~400 MHz, the system operation frequency is 350 MHz and the maximum measurement range is 0.857m.

　According to the specification of this circuit, we implement the transmitter, reciver, phase lock loop and phase detector with counter in the TMSC 0.18um CMOS process.If it can integrate for the whole system, it must provide a lot of contribution to science technique.

[1] A. Zolfaghari and B. Razavi, A low-power 2.4-GHz transmitter /receiver CMOS IC, IEEE J. of Solid-State Circuits, vol.38, NO.2, pp.176-183, Feb 2003. [2] Behzad Razavi, Design of Analog CMOS Integrated Circuits, ISBN：0071188398, Mcgraw-Hill, 2001.
[3] Behzad Razavi, RF Microelectronics, Prentice Hall PTR, 1997.
[4] B. D. Muer, M. Borremans, M. Steyaert and G. L. puma, A 2-GHz Low-phase-noise Integrated LC-VCO Set with Flicker-Noise Up conversion Minimization, IEEE J. of Solid-State Circuits, vol.35, NO.7, pp.1034-1038, July 2000.
[5] Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu, and Shen-Iuan Liu, New Dynamic Flip-Flops for High-Speed Dual-Modulus Prescaler, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 10, OCTOBER 1998.
[6] D. Ham and A. Hajimiri, Concepts and methods in optimizationof integrated LC VCOs ,IEEE Journal of Solid-State Circuits, pp. 896-909, June 2001.
[7] D. Ham and A. Hajimiri, Design and Optimization of a low-noise 2.4-GHz CMOS VCO with integrated LC tank and MOSCAP tuning, IEEE International Symposium on Circuits and Systems, vol. 1, Geneva, Switzerland, pp. 331-334, May 2000.
[8] DANIEL D. GAJSKI, PRINCIPLES OＦ DIGITAL DESIGN , CALIFORNIA UNIVERSITY ,1996.
[9] Derek K. Shaeffer, Thomas H. Lee, A 1.5-V, 1.5GHz CMOS Low Noise Amplifier, IEEE J. Solid-State Circuits, vol. 32, pp. 745-759, MAY.1997.
[10] Gardner, F, Charge-Pump Phase-Lock Loops, Communications, IEEE Transactions on [legacy, pre - 1988] , Volume: 28 , Issue: 11 , Pages:1849 –1858, Nov 1980.
[11] H.T. Friis, Noise Figure of Radio Receiver, Proc. IRE, Vol. 32, pp.419-422, July 1944.
[12] Herzel, F.; Razavi, B., A study of oscillator jitter due to supply and substrate noise, Circuits and Systems II: Analog and Digital Signal Processing, Volume: 46, Issue: 1 , Pages:56 – 62, Jan 1999.
[13] June-Ming Hsu, Guang-Kaai Dehng, Ching-Yuan Yang, Chu-Yuan Yang, Shen-Iuan Liu, Low-voltage CMOS frequency synthesizer For ERMES pager application, IEEE Transaction on Circuits and Systems II: Analog and Digital Signal Processing,Volume: 48, Issue: 9, Pages: 826 – 834, Sept 2001.
[14] Keen William, An analysis and performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase looked Loop Application Note 1001, National Semiconductor.
[15] Marc Tiebout, Low-power Low-phase-noise Differentially Tuned Quadrature VCO Design in Standard CMOS, IEEE J. of Solid-State Circuits, vol.36, NO.7, pp.1018-1024, July 2001.
[16] Michiel S. J. Steyaert; Bram De Muer; Paul Leroux; Marc Borremans, Low-Voltage Low-Power CMOS-RF Transceiver Design, IEEE Transactions On Microwave Theory And Technique, vol.50, NO.1, pp. 281-287, January 2002.
[17] Pan-Cheng Yu and Jin-Chuan Wu, A fully Integrated 3.3V 1- 600MHz CMOS Frequency Synthesizer, 1997 IEEE International Symposium on Circuits and Systems, pp.1828-1831, June 9-12 1997.
[18] R.Ludwig and P.Bretchko, RF Circuit Design: Theory and Applications,Prentice Hall, 2000.
[19] Steve C.Cripps, RF Power Amplifier for Wireless Communications, Artech House, 1999.
[20] Sergio Franco, Design with Operational Amplifiers and Analog Integrated Circuits, McGraw-Hill, 2001.
[21] Sungjoon Kim, A 960-Mb/s/pin Interface for Skew-Tolerant BusUsing Low Jitter PLL, Seoul National University, Taipei Hsien, vol.31, NO.5, pp.10-24, MAY 1997.
[22] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998.
[23] William Shing Tak Yan and Howard Cam Luong, A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator, IEEE Transactions On Circuits And Systems, vol.48, NO.2, pp.246-221, Feb 2001.
[24] Y.Imai, M.Tokumitsu and A.Minakawa, Design and performance of low-current GaAs MMIC for L-band front-end applications, IEEE Trans. Microwave Theory Tech, vol. 39, pp. 209-215, Feb. 1991.
[25] 于宗仁，應用在HDTV/ITV 寬頻帶射頻諧調器及900MHz/2.4GHz無線通 訊之頻率合成器的設計，國立成功大學電機工程研究所碩士論文，民 國八十六年。
[26] 江國維，應用光電感測技術與超外差式相位法之距離、震動、加速度量測系統，國立成功大學電機工程研究所碩士論文，民國91年。
[27] 邱永明，應用於2.4 及5.7GHz802.11WLAN 之CMOS 單晶射頻積體電 路，國立成功大學電機工程研究所碩士論文，民國九十二年。
[28] 紀宗億 無線心電圖通信晶片之研製，國立成功大學電機工程研究所碩 士論文，民國93年。
[29] 徐貞明，微波生醫遙測晶片之研製，國立成功大學電機工程研究所碩 士論文，民國92年。
[30] 黃秋皇，應用於IEEE802.11b/g 無線區域網路之2.4GHz CMOS 射頻接 收機，國立成功大學電機工程研究所碩士論文，民國九十二年。
[31] 劉沂娟，具有線性補償電路之2.4GHz 金氧半導體之射頻功率放大 器，國立交通大學電子研究所碩士論文，民國九十二年。
[32] 廖哲宏，應用於IEEE802.11a WLAN 之5.7GHz CMOS 射頻接收機 以及功率放大器RFIC，民國九十二年。
[33] 羅振斌 運用鎖相迴路技術實現無線心電圖之研究，國立成功大學電機工程研究所碩士論文，民國93年。