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研究生： 陳永宸
Chen, Yung-Chen
論文名稱： 透過動態分配單元擺放圍籬範圍之能感知圍籬區域限制數學解析擺置方法
A Fence Region Aware Analytical Placement Approach by Dynamic Allocating Cells to Fence Areas
指導教授： 林家民
Lin, Jai-Ming
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2023
畢業學年度： 112
語文別： 英文
論文頁數： 35
中文關鍵詞： 標準邏輯單元 、全局擺置演算法 、圍籬區域限制 、數學分析擺置公式 、多階層架構 、叢集 、實體設計
外文關鍵詞： Standard cell, Global placement algorithm, Fence region constraint, Analytical placement formulation, Multilevel framework, Cluster, Physical design
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    • 摘要 I Abstract II 誌謝 IV Table of Contents V List of Tables VII List of Figures VIII Chapter 1 Introduction 1 1.1 Motivation 2 1.2 Our Contribution 3 Chapter 2 Problem Formulation and preliminaries 5 2.1 Problem Formulation 5 2.2 Review of Dataflow-aware Analytical Placement Approach [10] 6 Chapter 3 Overview of Our Methodology 8 Chapter 4 Fence Region Aware Clustering 11 4.1 Clustering Under Fence Region Constraints 11 Chapter 5 Initial Global Distribution 14 5.1 Design flow of the Stage 14 5.2 Recursive Partitioning Procedure 15 5.3 QP with Zone Constraint 17 Chapter 6 Fence Region Aware Placement Refinement 18 6.1 Desirable Placement Region in Three Phase 18 6.1.1 First phase 18 6.1.2 Second phase 19 6.1.3 Third phase 19 6.2 Fence Region Aware Analytical Placement Formulation 20 Chapter 7 Acceleration of Our Program 23 7.1 Fixed Objects with Stable Locations 23 7.2 Partition of A Netlist Geometrically 24 Chapter 8 Experimental Results 26 8.1 Environment 26 8.2 Comparison with Effect of Techniques Applied in Our Methodologies 27 8.3 Comparison with The Previous Fence Region Aware Placer 29 8.4 Comparison with fence region aware wirelength model [8] 31 Chapter 9 Conclusion 33 Bibliography 34

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    [2] I. S. Bustany, D. Chinnery, J. R. Shinnerl, and V. Yutsis, “ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-routing-driven Placement,” in Proc. of ISPD, pp. 157–164, 2015.
    [3] T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “NTUplace3: An Analytical Placer for Large-scale Mixed-size Designs with Pre-placed Blocks and Density Constraints,” IEEE Trans. of TCAD, vol. 27, no. 7, pp. 1228–1240, 2008.
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    [7] J. Gu, Z. Jiang, Y. Lin and D. Z. Pan, “DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints,” in Proc. ICCAD, pp. 1–9, 2020.
    [8] C. -C. Huang et al., “NTUplace4dr: A Detailed-routing-driven Placer for Mixed-size Circuit Designs with Technology and Region Constraints,” IEEE Trans. of TCAD, vol. 37, no. 3, pp. 669–681, March. 2018.
    [9] M. R. Hestenes, and E. Stiefel, “Methods of Conjugate Gradients for Solving Linear Systems,” J. Res. Nat. Bur. Stand., vol. 49, no. 6, pp. 409-436, 1952.
    [10] J. -M. Lin, W. -F. Huang, Y. -C. Chen, Y. -T. Wang and P. -W. Wang, “DAPA: A Dataflow-aware Analytical Placement Algorithm for Modern Mixed-size Circuit Designs,” in Proc. of ICCAD, pp. 1–8, 2021.
    [11] J. -M. Lin, B. -H. Yu and L. -Y. Chang, “Regularity-aware Routability-driven Placement Prototyping Algorithm for Hierarchical Mixed-size Circuits,” in Proc. of ASPDAC, pp. 438–443, 2017.
    [12] J. -M. Lin, C. -W. Huang, L. -C. Zane, M. -C. Tsai, C. -L. Lin and C. -F. Tsai, “Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs,” in Proc. ICCAD, 2021.
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    [14] Peter Spindler, Ulf Schlichtmann, and Frank M. Johannes, “Fast Legalization of Standard Cell Circuits with Minimal Movement,” in Proc. of ISPD, pp. 47–53, 2008.

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