本論文為探討設計一個八位元的新型態時域類比數位轉換器。該時域類比數位轉換器分成類比與數位電路兩部分。類比電路包含取樣保持電路、電壓電流轉換器與電流驅動電路；數位電路囊括延遲電路、比較器、訊號選擇電路與解碼器。類比電路將輸入電壓訊號轉為電流訊號對電容充電，電容與其後端電路將產生步階訊號。時域類比數位轉換器就是在解調類比差動輸入訊號產生的步階訊號時間轉態點的差值得到轉換後的數位訊號。
由於類比電路架構簡單、功率消耗極低，因此時域類比數位轉換器整體的功率消耗不超過1 mW。透過使用差動電壓電流轉換器，可大幅提升時域類比數位轉換器可解調的輸入電壓範圍至1.6 Vp-p,diff。藉由游標卡尺延遲線的技巧，能夠設計出較小的時間單位，從而提升時域類比數位轉換器的操作頻率。最後使用粗調和細調的技巧，最小化延遲電路的使用，進一步減少晶片面積的使用。
在模擬中，論文提出的時域類比數位轉換器以耐奎斯特頻率輸入，能夠以奈奎斯特頻率達到訊號雜訊失真比45.9 dB，有效位元數7.34個位元的表現。在功率消耗0.97 mW的情況下，能得到其轉換效率為119 fJ/conversion-step。本論文嘗試以台積電180 nm 製程進行晶片的下線驗證。然而實際量測卻因為類比電路的電流偏離設計值，造成步階訊號的時間轉態點不在時脈訊號的工作週期，以致後續數位電路的部分無法正常操作因此晶片失效無法驗證模擬結果。

This thesis studies on a design of new-type, high speed and low power consumption time-based analog-to-digital converter（ADC）.The time-based ADC separates to two parts, analog and digital. The analog part includes sample and hold circuits, voltage-to-current converters and current-starved circuits. The digital part is composed of delay line circuits, comparators, signal selectors and decoders. The analog part converts the input voltage signal to a current signal which will charge a capacitor, so that the capacitor would generate a step signal. By modulating the difference between two transiton times of step signals which generated by the differential input signals, the time-based ADC converts the analog to the digital signal.
Due to the simple topology of the above mentioned analog cirucuit, the power consumption of time-based ADC is less than 1 mW. With such differential voltage-to-current converter, this time-based ADC can operate with higher input signal. By utilizing the skill of Vernier’s delay line, this time-based ADC can also demodulate with a smaller time unit, and increases the operating frequency. And the last, utilizing coarse and fine in timing demodulate can minimize the use of delay circuit and decrease the needs of chip area.
From simulation results, this time-based ADC can achieve SNDR 45.9 dB and ENOB 7.34 bits in Nyquist frequency. The time-based ADC consumes 0.97 mW power which leads to the a FoM of 119 fJ/conversion-steps. The chip is designed and fabricated by TSMC 180 nm. However, due to the current deviating from the design level, the transition times of step signals out of working cycles which leads to the wrong operation of digital circuit and thus making the chip failed.

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