| 研究生: |
李幸容 Li, Xing-Rong |
|---|---|
| 論文名稱: |
一個應用於觸控感測且具背景式校正能力的連續漸進逼近式類比數位轉換器陣列 A Background-Calibrated SAR ADC Array for Touch Sensing Applications |
| 指導教授: |
張順志
Chang, Soon-Jyh |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2024 |
| 畢業學年度: | 112 |
| 語文別: | 英文 |
| 論文頁數: | 97 |
| 中文關鍵詞: | 類比至數位轉換器 、逐漸趨近式時間至數位轉換器 、背景式校正 、偏移誤差校正 、增益誤差校正 |
| 外文關鍵詞: | analog-to-digital converter, successive approximation ADC, background calibration, offset error correction, gain error correction |
| 相關次數: | 點閱:43 下載:0 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文提出一個應用於觸控感測面板的十位元類比至數位轉換器陣列,其中每一個通道採用連續漸進逼近式架構以達到較低功耗,而為了確保通道之間效能的一致性,本設計針對通道之間的不匹配進行全晶片化背景式校正,在不影響類比至數位轉換器正常運作下加入少許電路達成錯誤偵測及校正。其中偏移誤差移除是採用輸入交換的概念達到兩次反向偏移誤差平均後相消。而增益誤差校正則採用交換參考電壓源後在比較器輸入端的殘值收斂情況來偵測錯誤,並調整參考電壓源以完成校正。
本設計以台積電90奈米CMOS製程進行晶片下線驗證,核心電路面積為0.393 〖mm〗^2。當晶片操作在每秒取樣一千六百萬次與電源電壓0.9伏特時消耗功率為3.29毫瓦,並得到奈奎斯特頻率的訊號雜訊失真比/有效位元56.03-dB/9.01位元,換算得到的轉換效率為56.8 fJ/conversion-step。
This thesis proposes a 10-bit analog-to-digital converter (ADC) array tailored for touch sensing applications, where each channel is realized by using a successive approximation architecture for pursuing lower power consumption. To ensure uniform performance across channels, the design incorporates on-chip background calibration for mismatches between channels, which is achieved by adding error detection and correction circuits without affecting normal ADC operation. Offset error removal employs the concept of swapping inputs to cancel offset errors through averaging in two opposite directions. Gain error correction uses the convergence of the residual value at the comparator input after exchanging the reference voltage source to detect errors, and adjusts the reference voltage source to complete the correction.
The design was verified using TSMC 90nm CMOS process, with a core circuit area of 0.393 mm2. Operating at a sampling rate of 16-MS/s and a supply voltage of 0.9 volts, the chip consumes 3.29 milliwatts of power. It achieves a signal-to-noise distortion ratio/effective resolution of 56.03 dB/9.01 bits at the Nyquist frequency. The corresponding conversion efficiency is 56.8 fJ/conversion-step.
[1] B. Murmann, “ADC Performance Survey 1997-2024,” [Online]. Available: https://web.stanford.edu/~murmann/adcsurvey.html
[2] C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010.
[3] V. Hariprasath, J. Guerber, S.-H. Lee, and U. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electron. Lett., vol. 46, no. 9, pp. 620–621, 2010.
[4] L. Deng, C. Yang, M. Zhao, Y. Liu, and X. Wu, “A 12- bit 200KS/s SAR ADC with a mixed switching scheme and integer-based split capacitor array,” in NEWCAS, 2013, pp. 1–4.
[5] B. Verbruggen, M. Iriguchi and J. Craninckx, “A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS,” in IEEE Journal of Solid-State Circuits,2012.
[6] C. -W. Hsu et al., “A 12-b 40-MS/s Calibration-Free SAR ADC,” in IEEE Transactions on Circuits and Systems I, 2018.
[7] B. Verbruggen, K. Deguchi, B. Malki and J. Craninckx, “A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS,” Symposium on VLSI Circuits Digest of Technical Papers, 2014.
[8] Y. Zhu et al., “Split-SAR ADCs: Improved Linearity With Power and Speed Optimization,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014.
[9] R. J. Van De Plassche, “Dynamic element matching for high-accuracy monolithic D/A converters,” IEEE J. Solid-State Circuits, vol. 11, no. 6, pp. 795–800, Dec. 1976.
[10] W. -H. Tseng, W. -L. Lee, C. -Y. Huang and P. -C. Chiu, “A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters,” in IEEE Journal of Solid-State Circuits, 2016.
[11] M. Ding, P. Harpe, Y. -H. Liu, B. Busze, K. Philips and H. de Groot, “26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme,” IEEE International Solid-State Circuits Conference, 2015.
[12] A. H. Chang, H. -S. Lee and D. Boning, “A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration,” ESSCIRC, 2013.
[13] R. Kapusta, J. Shen, S. Decker, H. Li, E. Ibaragi and H. Zhu, “A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS,” in IEEE Journal of Solid-State Circuits, 2013.
[14] M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, “A low-noise self-calibrating dynamic comparator for high-speed ADCs,” in IEEE A-SSCC, 2008, pp. 554–557.
[15] G. Blakiewicz, “Output-capacitorless low-dropout regulator using a cascoded flipped voltage follower,” in IET Circuits, Devices & Systems, vol. 5, no. 5, pp. 418-423, September 2011.
[16] L. Kull et al., “28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET,” IEEE International Solid-State Circuits Conference, 2017.
[17] C. -C. Liu et al., “A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” IEEE International Solid-State Circuits Conference, 2010.
[18] T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, Hao San and Nobukazu Takai, “SAR ADC algorithm with redundancy,” APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, 2008, pp. 268-271.
[19] G. Li, J. Guo, Y. Zheng, M. Huang and D. Chen, “Cascoded flipped voltage follower based output-capacitorless low-dropout regulator for SoCs,” 2015 28th IEEE International System-on-Chip Conference (SOCC), Beijing, China, 2015, pp. 368-373.
[20] A. Hastings, The Art of Analog Layout, 2nd Ed., Prentice Hall, 2006.
[21] R.-C. Liu, et al “Single mask metal-insulator-metal (MIM) capacitor with copper damascene metallization for sub-0.18 μm mixed mode signal and system-on-a-chip (SoC) applications,” in Proc. IEEE IITC, 2000, pp. 111–113.
[22] V. Tripathi and B. Murmann, “Mismatch characterization of small metal fringe capacitors,” in Proc. IEEE CICC, 2013, pp. 1–4.
[23] S. Haenzsche, S. Henker, and R. Schuffny, “Modelling of capacitor mismatch and non-linearity effects in charge redistribution SAR ADCs,” in Proc. IEEE MIXDES, 2010, pp. 300–305.
[24] C. -W. Hsu and S. -J. Chang, “A 1.6-GS/s 8b Flash-SAR Time-Interleaved ADC with Top-Plate Residue Based Gain Calibration,” 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-5.
[25] J. A. McNeill, C. David, M. Coln and R. Croughwell, “Split ADC Calibration for All-Digital Correction of Time-Interleaved ADC Errors,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 5, pp. 344-348, May 2009.
[26] G.-Y. Huang, S.-J. Chang, Y.-Z. Lin, C.-C. Liu, and C.-P. Huang, “A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS,” in IEEE A-SSCC. 2013, pp. 289−292.
[27] S. M. Jamal, Daihong Fu, N. C. -J. Chang, P. J. Hurst and S. H. Lewis, “A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration,” in IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1618-1627, Dec. 2002.
[28] Jaehun Jun,” 43 inch UHD Digital Kiosk System Using Advanced In-cell Touch Technology, SID 2018 DIGEST
[29] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, "A 10-bit Charge-Redistribution ADC Consuming 1.9 $mu$W at 1 MS/s," in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010.
校內:2026-12-31公開