本論文主要針對應用於低電壓供給低功率系統使用之資料讀取接收機射頻前端電路進行之研究與設計。由於現今隨著無線資料傳輸的需求逐漸增加，無線通訊系統無線通訊系統(wireless communication system)的發展及應用日漸成熟、廣泛。
車輛、工廠機器、人類對於諸如行動穿戴裝置、無線感測系統、物聯網以及應用於車輛安全系統的車輛間通訊協定的收發機制等等應用的需求日漸增加，而特定的應用裡如穿戴式產品、生理訊號及環境訊號監測的感測器係藉由太陽能、熱能或無線電波能量等方式供給能量的，其續航力必須長達數天至數年。
故在產品上的挑戰將著眼在高耐久的電源供應，其運算、接收之電路系統上將會強調其低功耗操作，以上述應用產品的續航力，這是目前以及未來發展的一項重要課題。作為此項應用之接收指令或資料更新的接收機必須擁有低功耗低電壓供給之重要特性。
本論文所設計的兩項接收機系統分別為：(1)提出以1.2伏作為供給電壓的接收機設計案，以達到低電壓供給、低功耗效能的目標，並且在頻段設定在應用範圍廣泛的ISM頻帶的2.4 GHz，將接收的2.4 GHz訊號經放大並解調變降頻至中頻段200 MHz。而操作頻段訂定在相對於人體為高頻的2.4 GHz，同時達到接收sensor與電路微小化。(2)提出以0.9伏作為供給電壓的接收機設計案，目的以達到較第一項設計案更低的供給電壓以及更低直流功率耗，並且將操作頻帶設計於1.8 GHz，此操作頻帶為LTE通訊協定中廣為手機電信營運商所採用之頻段。此接收機將1.8 GHz訊號做放大並解調變至中頻帶100 MHz。
本論文提出的射頻前端電路接收機系統主要係以四大子電路所構成，第一項為前端的低雜訊放大器，以高品質低雜訊的方式放大所接收的外部訊號。第二項是將前即所放大的訊號一轉二，提供兩個相位相差180度之巴倫器。三是混頻器，此級的操作是利用前級所接收的訊號與本地振盪源的訊號混頻後取降頻至中頻。考量混頻器若使用單平衡式架構必需使用帶通濾波器以降低LO的feed through訊號對IF訊號的干擾；而本論文提出此系統架構在混頻前將射頻訊號經由主動式巴倫器將單端訊號轉為雙端訊號(而其中主動式巴倫器較被動式巴倫器省面積)，故使用能於差動輸出消減LO的feed through 所造成的干擾的雙平衡式之架構，且能較單平衡式混頻器提供射頻訊號多一級增益。第四級為最後一項電路，是作為量測考量用的二轉一量測緩衝器，將降頻的訊號輸出至輸入阻抗為50 Ohm之儀器量測。兩項晶片製程係使用國家晶片中心(CIC)提供的TSMC 0.18-µm 1P6M RF CMOS標準製程進行設計及布局，並利用PCB印刷電路板(Chip on board)方式進行量測。

The aim of this thesis is to design low voltage RF front-end receivers, to achieve a low voltage supply and low power consumption system for wireless communication system.
This thesis includes two receiver system designs at two chip implementations: a 1.2V, 2.4 GHz receiver and a 0.9V, 1.8GHz receiver, respectively. Both direct conversion receivers include four function blocks: The first function block of the receiver is a low noise amplifier (LNA) amplifying the signal with high quality and low noise.

The second function block of the receiver, balance to unbalance (Balun) converter, converts signal form single ended to differential output in same conversion gain.

The third function block of the receiver is mixer, this function block translates input RF frequency signal to output IF frequency signal by multiplying RF frequency signal with local oscillator (LO) signal, and the process is called down-conversion. At least, this thesis adopts measurement buffer in the fourth function block of the receiver, this stage’s function transfers differential baseband output into single signal for the 50 Ohm input impedance measurement instrument to measure. In addition, all designs mentioned above are all fabricated by TSMC 0.18-μm RF CMOS process.

According to the measurement results, the sensitivity of 1.2 V, 2.4 GHz receiver can be detected by input signal power level is -50 dBm. And also the 0.9 V, 1.8 GHz front end receiver circuit, input signal level in -40 dBm is still detectable.

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