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研究生： 余曜廷
Yu, Yao-Ting
論文名稱： 應用於癲癇辨識演算法之RISC-V專用指令集處理器設計
An Application Specific Instruction-set Processor Based on RISC-V for Epilepsy Identification Algorithm Hardware Design
指導教授： 李順裕
Lee, Shuenn-Yuh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2019
畢業學年度： 108
語文別： 中文
論文頁數： 95
中文關鍵詞： 處理器 、RISC-V 、專用指令處理器 、嵌入式 、穿戴式 、邊緣運算 、低功耗 、edge
外文關鍵詞： processor, IoT, embedded device, wearable device, edge processing, ASIP, RISC-V, low power, epilepsy
相關次數： 點閱：83  下載：1 
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    • 本論文提出一個應用於癲癇偵測及癲癇辨識演算法的專用指令集處理器(Application-Specific Instruction-set Processor, ASIP)硬體架構，基於RISC-V指令集架構(Instruction Set Archetecture, ISA)進行設計。其中辨識癲癇演算法為人工智慧(Artificial Intellegence,AI)的卷積神經網路(Convolution Neural Network, CNN)演算法，其流程為腦波訊號採集、腦波訊號預處理、特徵萃取(Feature extraction)、類神經網路(Neural network)分類器，先將收集到的腦波進行濾波後，經由特徵萃取給予分類器特徵值進行分類，最終輸出辨識結果。訊號取樣頻率為250Hz。由於每個個體間的腦波略有差異，因此採用具學習能力的類神經網路架構進行分類，可使演算法更適用於不同個體的腦波上，以提升精準度。此外，本論文題出一個應用於癲癇辨識之專用指令集處理器(Application Specific Instruction-set Processor, ASIP)，且基於RISC-V指令集架構與此癲癇辨識所設計之ASIC進行架構整合，並與RSIC-V通用指令集處理器RV32I三者做比較，此架構與通用型處理器相比有較高的處理效能，對此癲癇偵測演算法有725.9%之加速，與ASIC相比，此架構有可程式化之功能，不僅能做為系統核心控制器，處理此演算法可以達到即時(real-time)的運算，未來對於此架構進行軟體開發，也可以用來加速運算其他不同的CNN演算法以達多功能應用的目的，因此此架構為最適合用來作為穿戴式裝置健康照護系統之核心架構。

    With the booming development of smart devices, the demand for mobile devices as Internet of Things (IoT) has increased dramatically in recent years. At a time when the popularity of mobile devices is growing rapidly, smartphones are no longer confined to young people. More and more, elder people are joining the trend. Therefore, in the aging society, combining the two concepts of wearable devices and the IoT to construct an action wearable health care system to achieve the objective of monitoring physiological signals in anytime and anywhere. It is a development direction with great market potential.
    And among a lot of disease, epilepsy is a disease that cause people to suffer from uncertain seizure, thus a wearable health care system that can offer seizure detection will be suitable for people suffer from epilepsy, only if the seizure is detected directly can the measures be taken instantly to take people out of danger.
    To achieve a complete wearable health care system, it needs to complete the important blocks including special design textile material electrode, physiological signal sensing circuit, analog-to-digital converter circuit, signal processing circuit or microprocessor, power management circuit. But the most important core unit in this system is the microprocessor which is intended to control the different units in the system and also process the signals derive from the sensors, so the processor has to achieve low power consumption and also have the processing performance to process the data efficiently.

    摘要 II 致謝 IX 目錄 X 表目錄 1 圖目錄 2 第一章 緒論 4 1.1 研究背景 4 1.2 研究動機與目的 4 1.3 相關探討 5 1.4 論文架構 7 第二章 專用指令集處理器介紹與設計 8 2.1 常見運算處理單元架構介紹 8 2.1.1 通用型處理器(GPP) 8 2.1.2 專用指令集處理器(ASIP) 8 2.1.3 特殊用途積體電路架構(ASIC) 9 2.1.4 架構優缺點比較 9 2.2 專用指令集架構處理器原理及架構 10 2.3 RISC-V指令集架構簡介 12 2.2.2 指令集簡介 14 2.2.3 可配置的通用暫存器組 16 2.2.4 指令編碼 16 2.2.5 記憶體存取指令 17 2.2.6 分支轉跳指令 18 2.2.7無分支延遲槽 19 2.2.8壓縮指令 19 第三章 專用指令處理器架構設計 21 3.1 專用指令集處理器設計 21 3.2 癲癇介紹 23 3.3 癲癇偵測演算法 23 3.3.1 Z-score normalization 25 3.3.2 CNN 27 第四章 處理器架構 30 4.1 記憶體架構 31 4.2 Pipeline 32 4.1.1資料相依 33 4.3 指令擷取單元(Instruction Fetch unit, IFU) 37 4.2.1分支跳躍指令以及預測 40 4.4 運算單元(Execution Unit, EXU) 44 4.2.1資源衝突 45 4.2.1算數邏輯運算單元ALU 46 4.5 bootloader 47 第五章 AI指令集硬體加速器 49 5.1 Z-score 標準化 50 5.1.1 Mean instruction 52 5.1.2 Square instruction 54 5.1.3 Mean square instruction 56 5.1.4 z-score instruction 58 5.2 卷積神經網絡(Convolutional Neural Network, CNN) 61 5.2.1 Convolution 62 5.2.2 Max pooling instruction 65 5.2.3 ReLU instruction 68 5.3硬體消耗 71 5.4加速(speed-up) 72 第六章 驗證考量與結果 74 6.1 處理器電路驗證 74 6.1.1 Accuracy and loss 77 6.1.2 FPGA驗證 80 6.1.3 規格表 88 第七章 結論與未來展望 90 參考文獻 91 口試委員意見回覆 93

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