本論文設計為應用於2.4-/24-GHz雙頻帶共存接收機之子電路設計，其中可分為兩個部分：第一部分為K-band變壓器回授壓控振盪器；第二部分為2.2 GHz ISM-band 非整數型鎖相迴路。在本論文中設計之兩個子電路皆使用TSMC 0.18 µm CMOS製程實現。
在K-band變壓器回授壓控振盪器設計中，變壓器之主線圈利用單線圈與較大線寬降低寄生電阻以提升品質因子。變壓器主線圈接至電晶體的汲極與電容形成共振腔，次線圈接至電晶體源極。由於汲極與源極為同相位關係，透過變壓器增加輸出擺幅，達到高輸出功率與低相位雜訊。在本次設計電路之量測結果，頻率可調範圍為21.53~2.2 GHz；量測相位雜訊在21.6 GHz偏移1 MHz處為-102.08 dBc/Hz，偏移10 MHz處為-126.83 dBc/Hz；輸出功率皆大於-6.01 dBm，功率消耗為11.74 mW。包含緩衝放大器之整體晶片面積為0.665 mm2。
在2.2 GHz非整數型鎖相迴路中，子電路包含相位頻率偵測器(PFD)、充電泵(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、多模數除頻器(MMD)及三角積分調變器。藉由數位輸出控制多模數除頻器，在一段時間內變化除頻器除數，達到平均除小數之概念，改善頻寬與頻道間距的取捨關係。因三角積分調變器將除數隨機化的關係，降低其小數突波之大小。在本次設計電路之量測中，參考訊號頻率設定為20 MHz，量測其輸出訊號頻率為2.18 GHz至2.45 GHz；相位雜訊在2.213 GHz偏移10 MHz處為-125 dBc/Hz；輸出功率皆大於-7.26 dBm，功率消耗為18.9 mW。包含緩衝放大器之整體晶片面積為1.13 mm2。

The thesis proposes the subcircuit designs of 2.4-/24-GHz coexistence RF receiver Front-end circuits. There are two parts. The first part is about the design of the K-band transformer feedback voltage-controlled oscillator. A 2.2 GHz fractional-N phase-locked loop is designed in the second part. All the above-mentioned designs are fabricated in TSMC 0.18 µm CMOS process.
In the design of the K-band transformer feedback voltage-controlled oscillator, asymmetric-width transformer is applied to improve the quality factor of LC tank. Since the waveforms of the drain and the source are in-phase, the output amplitude is enhanced through the transformer coupling effect and therefore, achieves greater phase noise. From the measurement results of this design circuit, the measured frequency tuning range is 21.53 ~ 2.2 GHz; the measured phase noise is -102.08 dBc/Hz at the 1 MHz offset from the center frequency of 21.6 GHz carrier frequency. The proposed VCO dissipates 11.74 mW, and the overall chip area including the buffer amplifiers is 0.665 mm2.
In the design of the 2.2 GHz fractional-N phase-locked loop, including a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a multi-modulus divider and a delta-sigma modulator are involved. By dithering the division ratio, a fractional divider is implemented, and it achieves high bandwidth and fine frequency resolution. From the measurement results of the proposed fractional-N PLL, the reference frequency is set to 20 MHz, the measured frequency tuning range is 2.18 GHz to 2.45 GHz. The measured phase noise is -125 dBc/Hz at the 10 MHz offset from the center frequency of 2.213 GHz, and the output power is above -7.26 dBm. The proposed PLL dissipates 18.9 mW and occupies an area of 1.13 mm2.

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