漣波控制模式常受到電壓穩定度、操作頻率變動問題所困擾，常見的做法多以類比電路改善，然而類比電路必須面對製程飄移而導致的設計偏差現象。數位電路的優勢在於只要高低準位仍可正常判定電路就能正常動作，具有較強的可靠性。此外，其抗雜訊能力強且具有較高的靈活性等特點也逐漸受到重視。本文以FPGA ADC-SoC開發板與PCB電路分別實現數位控制與功率級電路來驗證此降壓轉換器之功能。功率級輸入電壓與輸出電壓分別為4.2V與1.2V，在負載電流變動範圍為100mA~800mA下，加入定頻機制使操作頻率範圍限縮至500~515kHz，操作頻率變動差由23.9%降至3%。數位暫態加速機制縮短升載與降載的安定時間至10μs以內，上衝電壓與下衝電壓分別減少至110mV與68mV。

The Ripple-based Buck converter frequently experiences circuit instability and operational frequency variations. Typically, analog circuitry is used to address these issues. However, the performance of the analog circuits are prone to pa-rameter drift under the manufacturing process. In this context, the benefits of digital circuits become evident as they offer strong noise immunity and high flexibility, which are significant advantages. This study demonstrates the func-tionality of a ripple-based Buck converter by implementing digital control us-ing an FPGA on a PCB power stage. The input voltage was 4.2V, while the output voltage was 1.2V. With a load current ranging from 100mA to 800mA, the operating frequency of the buck converter is limited to 500-515kHz, re-sulting in a decrease in switching frequency variation from 23.9% to 3.0%. Additionally, the digital transient acceleration mechanism reduces settling time to within 10μs and effectively decreases overshoot voltage to 110mV and un-dershoot voltage to 68mV.

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