隨著"More-than-Moore" (MtM)理念的提出，半導體技術的發展不僅僅局限於摩爾定律所推動的電晶體尺寸縮小。MtM強調透過整合其他技術來擴展半導體領域的應用範圍。而射頻(RF)技術是其中一項重點發展領域。因此，隨著RF需求增長，如何優化元件結構以提升其射頻性能成為了研究的重點。
本論文旨在透過數值模擬調整製程參數和元件結構來充分發揮RF FinFET的發展空間。研究主要集中在以下三個方面：首先是gate spacer的結構優化，我們將探討使用不同材料(如Si3N4和HfO2)以及single-k和dual-k對結構特性的影響。其次，調整擊穿停止層(PTSL)的摻雜濃度，以及通道長度的變化。我們將研究摻雜濃度範圍從1e18到7e18 cm-3的變化，和測試通道長度在30 nm縮短到18 nm時的表現，並找出最佳摻雜濃度及通道長度，以平衡導通電流、漏電流和整體RF performance等問題。最後，觀察在溫度300 K到100 K下的元件特性，我們將探討在低溫環境下操作FinFET是否能進一步提高其射頻性能，如fT (cut-off frequency)和fMAX (Maximum oscillation frequency)等關鍵指標。透過這些研究，我們期望能提供有效的方法來提升RF FinFET的性能，以滿足未來高頻應用的需求。

With the introduction of the "More-than-Moore" (MtM) concept, the development of semiconductor technology is no longer limited to the reduction of transistor size driven by Moore's Law. MtM emphasizes the integration of other technologies to expand the application range of the semiconductor field. Radio Frequency (RF) technology is a key area of focus within this context. Therefore, with the growing demand for radio frequency applications, optimizing device structures to enhance RF performance has become a significant research focus.
This thesis aims to fully exploit the potential of RF FinFET development through numerical simulation, which is adjusting process structures and parameters. The research focuses on the following three aspects: First, the optimization of the gate spacer structure. We will investigate the effects of using different materials (such as Si3N4 and HfO2) and single-k and dual-k configurations on the structural properties. Second, the adjustment of the Punch Through Stop Layer (PTSL) doping concentration and the variation in channel length. We will study the impact of doping concentrations ranging from 1e18 to 7e18 cm-3, and test the performance as the channel length is reduced from 30 nm to 18 nm. The goal is to identify the optimal doping concentration and channel length to balance leakage current, total current, and overall RF performance. Finally, by examining device characteristics at temperatures ranging from 300 K to 100 K, we will explore whether operating FinFETs in low-temperature environments can further enhance their RF performance. Through these studies, we aim to provide effective methods to improve the performance of RF FinFETs to meet the demands of future high-frequency applications.

[1] G. E. Moore, "Cramming more components onto integrated circuits, Reprinted from Electronics, volume 38, number 8, April 19, 1965, pp.114 ff," IEEE Solid-State Circuits Society Newsletter, vol. 11, no. 3, pp. 33-35, 2006.
[2] V. Subramanian et al., "Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective," IEEE Transactions on Electron Devices, vol. 53, no. 12, pp. 3071-3079, 2006.
[3] M. Graef, "More Than Moore White Paper," in 2021 IEEE International Roadmap for Devices and Systems Outbriefs, 2021, pp. 1-47.
[4] G. Q. Zhang, F. v. Roosmalen, and M. Graef, "The paradigm of "more than Moore"," in 2005 6th International Conference on Electronic Packaging Technology, 30 Aug.-2 Sept. 2005 2005, pp. 17-24, doi: 10.1109/ICEPT.2005.1564646.
[5] M. Xu et al., "Improved Short Channel Effect Control in Bulk FinFETs With Vertical Implantation to Form Self-Aligned Halo and Punch-Through Stop Pocket," IEEE Electron Device Letters, vol. 36, no. 7, pp. 648-650, 2015, doi: 10.1109/LED.2015.2434825.
[6] R. K. Ratnesh et al., "Advancement and challenges in MOSFET scaling," Materials Science in Semiconductor Processing, vol. 134, p. 106002, 2021/11/01/ 2021, doi: https://doi.org/10.1016/j.mssp.2021.106002.
[7] E. Team. "7 Pillars of TSMC Roadmap to Chip Supremacy Till 2030." Techo Vedas. https://reurl.cc/ez7XYj (accessed June 11, 2024).
[8] J. Singh et al., "14-nm FinFET Technology for Analog and RF Applications," IEEE Transactions on Electron Devices, vol. 65, no. 1, pp. 31-37, 2018, doi: 10.1109/TED.2017.2776838.
[9] CMOS RF Modeling, Characterization and Applications (Selected Topics in Electronics and Systems Series Volume 24). WORLD SCIENTIFIC, 2002, p. 424. Accessed: 2024/06/10. [Online]. Available: https://doi.org/10.1142/4921.
[10] J. Dunsmore, "Handbook of Microwave Component Measurements: with Advanced VNA Techniques," 2012.
[11] W. Chakraborty et al., "Characterization and Modeling of 22 nm FDSOI Cryogenic RF CMOS," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 7, no. 2, pp. 184-192, 2021, doi: 10.1109/JXCDC.2021.3131144.
[12] S. O. Kasap, Electronic materials and Devices. McGraw-Hill New York, 2006.
[13] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration," IEEE Transactions on Electron Devices, vol. 41, pp. 2357-2362, 1994.
[14] A. Beckers, F. Jazaeri, and C. Enz, "Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors," IEEE Electron Device Letters, vol. 41, no. 2, pp. 276-279, 2020, doi: 10.1109/LED.2019.2963379.
[15] "International Roadmap for Devices and Systems (IRDS™) 2018 Edition." https://irds.ieee.org/editions/2018/more-moore (accessed June 11, 2024).
[16] Synopsys, "SentaurusTM Device User Guide," Version T-2022.03, March 2022.
[17] Synopsys, "SentaurusTM Visual User Guide," Version T-2022.03, March 2022.
[18] K. I. Seo et al., "A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI," in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 9-12 June 2014 2014, pp. 1-2, doi: 10.1109/VLSIT.2014.6894342.