本論文提出一個可應用於多標準視訊解碼中動態補償之可重組內插補點架構設計，設計目標主要在於MPEG-2、MPEG-4、和H.264這三個視訊編碼標準，透過分析目標標準中動態補償的演算法，我們找出彼此的共性和相似處，並經由探索設計空間，我們設計出一套規則的資料流和一套可重組化的處理元件提供所有情況下需要的運算，考慮到H.264的頻寬瓶頸，我們使用基本的降低頻寬策略幫助減少記憶體存取次數。為了確認設計的正確，我們使用一套階層式的驗證計畫去驗證，所提出的硬體架構是利用TSMC 0.18um製程合成，操作頻率為108百萬赫茲，可支援解析度為1920x1088、30frames/sec的即時處理要求。此外，比起將三個目標標準中內插補點的面積相加，最後的合成結果顯示，我們所提出的架構在面積上有顯著的減少。

In this thesis, we propose a reconfigurable architecture design of motion compensation for multi-standard video coding. The targeted application is focused on three popular video standards—MPEG-2, MPEG-4, and H.264. Through top-down design methodology, we analyze the motion compensation algorithm of the targeted standards, and figure out the commonality of motion compensation algorithm among the three standards. Continuously, we explore the design space and then arrange a regular data flow which is suitable to each standard, and also design a reconfigurable processing element to perform the required operation in various cases. Considering the bottleneck of bandwidth in H.264, we apply the basic bandwidth reduction strategies to reduce the memory access time. To ensure the correctness of the design, a hierarchical level verification plan is performed. The implementation of proposed architecture is synthesized with TSMC0.18 um technology library. The operating speed is set to 108MHz and can support the real time motion compensation coding of 1920x1088 at 30 frames per second in MPEG-2, MPEG-4, and H.264. The synthesized result also shows our work have significant reduction in area compared with summing-up the interpolator of all three standard independently.

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