本論文主要為CMOS功率放大器的研究。在射頻傳送機前端電路中，功率放大器是一很重要的元件，其將來自基頻的訊號依應用系統需求來放大，並提供給天線傳送出去。
在現今的無線通訊系統，積體化一直是長久被討論的方向。使用CMOS製程最大的優點為以較低的成本並可以完整的與後端基頻系統電路整合。設計的電路使用在Mobile WiMAX 802.16e，其傳輸頻寬為3400MHz到3700MHz。
在本篇論文中，將提出之CMOS功率放大器設計皆利用推挽式放大器差動技術抑制偶次諧波，並使用電晶體基板偏壓來抑制電晶體基板效應，使得功率放大器的線性度及效率獲得提升。而利用不同的功率結合技術提出包含以下三個電路。
在3.5 GHz全整合式變壓器功率放大器設計中，設計晶片式變壓器作為電路輸入端的差動訊號產生及輸出功率結合，其最大功率輸出23.6 dBm時有28%的PAE，線性輸出功率(Pout @ P1dB)在 20.5 dBm時有17%的PAE，功率增益為(Gain)11.6 dB，輸出三次交互調變點(OIP3)為32dBm。
在3.5 GHz採用並聯放大技術功率器設計中，沿用變壓器作為電路輸入端的差動訊號產生，於輸出部分採用lattice-balun技術作為功率結合，其最大功率輸出25 dBm時有41.8%的PAE，線性輸出功率(Pout @ P1dB)在 22.4 dBm時有30%的PAE，功率增益為(Gain)11.6 dB，輸出三次交互調變點(OIP3)為30dBm。
最後使用兩階功率放大模組並模擬送入WiMAX訊號的狀態驗證，完成達到符合Mobile WiMAX應用的高功率CMOS射頻功率放大器設計。其線性輸出功率在28.4dBm時33.6%的PAE。
本論文中的電路設計是使用TSMC 0.18 um CMOS製程model並搭配Aglient ADS軟體進行電路模擬及電磁分析，透過CIC下線而完成晶片的製作，最後於CIC進行相關量測及驗證。

In this thesis, high-power CMOS power amplifier modules are investigated. In radio-frequency (RF) transmitter front-end, power amplifiers are an important component. Power amplifiers can amplify base-band signals and then transport them into an antenna for wireless communication system.
The integration of wireless communication systems has taken a long journey into the modern world. The feature of CMOS processing technology is fully integrated with base-band system and the cost is cheaper. It is designed to operate in the application of Mobile WiMAX 802.16e band, which has the operation frequency ranging from 2400MHz to 2700MHz.
In this thesis, a differential push-pull topology is used to suppress even-order harmonics, and an adopting substrate bias topology can greatly reduce the body effect, the efficiency and linearization can be improved. We design three circuits of CMOS power amplifier with differ power combing topology.
In the first design, 3.5GHz transformer-integrated RF power amplifier, we designed the on-chip transformer to split input signal and combine output signal. The circuit is capable of delivering 23.6dBm of maximum output power with an 28% power-added efficiency and 20.5dBm of linear output power with 17% PAE. The power gain is 11.6dB, and the output third-order intercept point is 32dBm.
In the second design, a power module is like as the first circuit except that the output on-chip transformer is replaced by LC resonators. The circuit is capable of delivering 25dBm of maximum output power with an 41.8% power-added efficiency and 22.4dBm of linear output power with 30% PAE. The power gain is 11.6dB, and the output third-order intercept point is 30dBm.
At last, we have simulated and tested high-power CMOS RF power amplifier by combining with two power modules in parallel for mobile WiMAX application. This power amplifier is capable of delivering 28.4dBm of linear output power with 33.6% power-added efficiency and fit in with specification of mobile WiMAX.
With EM simulation of Aglient ADS, the influence of lines in the layout can be considered. The circuits are implemented by TSMC 0.18um CMOS process. These chips have also been fabricated and measured by the support of CIC in Taiwan.

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