傳統上多核心系統是以匯流排(bus)作為互聯(interconnect)，它的傳遞延遲較低。但是它一次只能服務一個核心(core)，隨著core的數量越來越多，它便開始成為效能上的瓶頸。因此，有人提出晶片網路(Netwok on Chip, NoC)作為多核心系統的interconnect。由於以NoC為interconnect的多核心系統廣播(broadcast)較為困難，無法以傳統bus上的偵聽式協定(snoop-based Protocol)去維持快取一致性(cache coherency)。因此，在NoC上多採用目錄式協定(directory-based protocol)去維持晶片上的cache coherency。
在本論文中，我們以SystemC語言實作NoC的時間近似模型(approximate-timed model)，將其應用於多核心平台，並且在NoC上實作MESI directory-based cache coherence protocol，並且以此平台針對SPLASH-2驗證程式(benchmark)進行分析。此外，我們提出了一種混合式互聯(hybrid interconnect)以減少NoC上的traffic。我們以SPLASH-2對此hybrid interconnect進行效能評估，實驗結果顯示，相較於8核、16核，以及32核的純NoC-based interconnect，traffic分別可以減少53%,45%與39%。

Traditionally, a bus interconnect is used as the interconnect in a multi-core system due to its low transmission delay. However, it can only serve one master core at a time, and thus becomes a bottleneck when the number of cores increases in the system. Therefore, Network-on-Chip (NoC) is proposed as the interconnect of a many-core platform. In a NoC-based many-core system, broadcast is costly, so we can’t apply the snoop-based cache coherence protocol to maintain the cache coherency. For this reason, a directory-based cache coherence protocol is commonly used for on-chip data coherency.
In this thesis, we use SystemC to implement an approximate-timed model of NoC, and realize the MESI directory-based cache coherence protocol. In addition, we develop a hybrid interconnect by clustering a small number of cores using bus to reduce the traffic in the NoC. We evaluate it by executing the SPLASH-2 Benchmarks. According to the experimental results, the hybrid internconet can reduce the traffic in the NoC by 53%, 45%, and 39% respectively with 8, 16, and 32 cores compared to the baseline without clustering.

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