可暫停且恢復系統運作之矽除錯技術可將電路的時脈暫停運作，進而取得暫存器的內部狀態讓使用者進行觀察，再恢復電路時脈以進行更進一步的除錯流程。資料無效是使用此多時域除錯技術時可能會發生並且需注意的問題；資料無效是當接收端時域中的暫存器在除錯期間捕捉到不正確的數據，而造成系統無法正確地恢復運作。在此論文中，我們提出了一種新穎的矽除錯技術，可在任一時脈週期暫停電路並且可避免捕捉到錯誤的數據。我們可以讓使用者自行設定欲觀察的中斷點，再利用軟體來計算需發送暫停控制信號的確切時間，並且開發相應的硬體控制器以將暫停信號轉換成用於待除錯電路和跨時域數據傳輸介面的時脈控制信號。因此，我們可以避免資料無效的問題並允許使用者在任意的時脈週期暫停待除錯電路且能正確的回復電路的運行。由實驗結果來看，我們的矽除錯技術所需的硬體面積非常小，並且能達到100%的除錯觀察率。

The run-pause-resume (RPR) debug methodology allows one to pause the normal circuit operations, observe the internal states of flip-flops and then resume the normal operations for further debug process. Data invalidation is a major problem that needs to be addressed when debugging a multiple-clock design with this methodology. This problem occurs when flip-flops in a receiving clock domain capture incorrect data during debugging, and thus cannot be resumed correctly. In this thesis, we propose a novel RPR technique that can avoid data invalidation with the cycle-level granularity of debug resolution. A software program is employed to calculate the exact time to transmit pause control signals according to the user-defined breakpoint and a hardware controller is developed to convert the pause signal to appropriate gating signals for the circuit under debug (CUD) and the data path of the clock domain crossing interface. By doing this, we can avoid data invalidation as well as allow users to pause and resume the CUD at arbitrary clock cycle. Experimental results show that the hardware area overhead is very small and 100% debug resolution is achieved.

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