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研究生： 郭珏攸
Kuo, Chueh-Yu
論文名稱： 利用CMOS製程設計應用於毫米波之慢波結構縮小化被動元件
On-Chip Compact Passive Devices with Slow-Wave Structure in CMOS Process for Millimeter-Wave Applications
指導教授： 羅錦興
Luo, Ching-Hsing
共同指導教授: 李致毅
Lee, Jri
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2011
畢業學年度： 99
語文別： 英文
論文頁數： 69
中文關鍵詞： CMOS 、分支線耦合器 、威爾金森功率分配器／合成器 、慢波
外文關鍵詞： CMOS, Branch-line coupler, Wilkinson Power Divider/Combiner, Slow-wave
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    • 本論文提出一系列利用慢波結構實現於CMOS製程的縮小化微波被動元件，主要分為兩個部分，第一個部分是利用CMOS 90 nm digital process 製程一個具有90°相位差的分支線耦合器，結合慢波結構以及共平面波導的方式，達到縮小晶片面積的效果;第二部分則是利用CMOS 90 nm RF process製作而成的威爾金森功率分配器/合成器，此研究的波導方式採用elevated-center 共平面波導的方式來設計，此波導方式可以很容易達到所要的阻抗值且方便平衡兩側接地面的電位進而減少高階模態的產生，最後再將慢波結構加入信號線中，以及製程廠所提供的電阻模型，完成此設計。
    90°相位差的分支線耦合器利用一些位於信號線下方的慢波結構，提高介電常數，進而可以使波所行走的長度變短面積縮小，減少晶片成本，此設計的量測結果在60 GHz時的插入損耗為2.8 dB，隔離度為25dB，四個埠之反射損耗大於10 dB的頻寬範圍低頻從46 GHz起，高頻則可超過67 GHz，振幅不平衡60 GHz時0.8 dB，相位不平衡60 GHz 時90.3°，晶片面積不含pad為290 μm× 285 μm，與傳統的架構面積比起來可減少約75 %。
    威爾金森功率分配器/合成器利用在信號線上加入慢波結構，並將其原本兩側的接地面下降一層金屬，此效果可以在傳輸線轉折處直接拉金屬線將兩側的接地面電位保持平衡，而減少高階模態的產生，也減少via的使用，另外也可輕易的達到高阻值的傳輸線，而慢波的結構，也是可以縮小面積減少波所走的長度，減少成本開銷。此設計量測結果的插入損耗在60 GHz時為2.4dB，兩輸出埠的隔離度在77 GHz時為13.7 dB，反射損耗為14.2 dB，振幅不平衡在60 GHz時為0.068 dB，相位不平衡60 GHz 時0.453°，晶片面積不含pad為250 μm × 350 μm.，與傳統的架構面積比起來可減少約80 %。

    The thesis proposed two parts of compact passive devices in CMOS process for millimeter-wave applications. The first part is a 90° branch-line coupler with slow-wave structures and coplanar waveguide (CPW) in CMOS 90 nm digital process. The occupied area can be decreased because of the method. The other one is Wilkinson Power Divider / Combiner with slow-wave structures and elevated-center coplanar waveguide (EC-CPW) in CMOS 90 nm RF process. EC-CPW can be achieved the impedance value what we want easily and suppress the high order mode. Then combine the slow-wave signal line and the resistor model from foundry to complete the design.
    The slow-wave structures of the 90° branch-line coupler that is located beneath the signal line can increase the effective dielectric constant so that the effective wavelength and the area can be decreased. The measured result of insertion loss (IL) is 2.8 dB at 60 GHz. The measured isolation is 25 dB. The return losses (RL) of four ports are over 10 dB from 46 GHz to at least 67 GHz. The amplitude imbalance is 0.8 dB at 60 GHz. The phase difference is 90.3° at 60 GHz. The occupied are without pads is 290 μm× 285 μm and lower about 75 % than a conventional one’s.
    The novel Wilkinson Power Divider / Combiner mainly utilizes an elevated-center slow-wave signal line to complete it. The lower ground metal layer besides the signal line can be connected directly without via and suppress the high mode at the meander locations. And the slow-wave signal line also decreased the area. The measured IL is 2.4 dB at 60 GHz. The measured isolation and RL of two output ports are 13.7 dB at 77 GHz and 14.2 dB, respectively. The amplitude imbalance and phase difference are 0.068 dB and 0.453° at 60 GHz separately. The chip area with pads is 250 μm × 350 μm and is smaller about 80 % than an area of conventional Wilkinson Power Divider / Combiner.

    Contents viii List of Tables X List of Figures XI Chapter 1 Introduction 1 1.1 Introduction and Motivation 1 1.2 WPAN Introduction 3 1.3 Thesis Organization 4 Chapter 2 Slow-Wave Structure Theory 6 2.1 Introduction 6 2.2 Literature Review 8 2.3 Slow-Wave Structure 10 2.4 Simulated Verify 11 2.4.1 The basic effects in transmission line 12 2.4.2 The variation for the length of slow-wave structures 15 2.4.3 The variation for gap width of CPW signal line 16 2.4.4 The variation for width of slow-wave structures 17 2.4.5 The variation for spacing width of slow-wave structures 18 2.5 Conclusion 19 Chapter 3 60 GHz Slow-Wave Branch-line Coupler 20 3.1 Introduction & Motivation 20 3.2 Branch-line Coupler Theory and Analysis 21 3.2.1 Prototype Branch-Line Coupler 21 3.2.2 Branch-Line Coupler Analysis 22 3.2.3 The Process Model in HFSS 25 3.3 The Slow-wave Branch-line Coupler Design and Measurement 26 3.3.1 The simulation results for the slow-wave branch-line coupler 28 3.3.2 The measurement results for the slow-wave branch-line coupler 32 3.4 Discussion and Conclusion 36 Chapter 4 60 GHz Slow-Wave Meander Branch-Line Coupler 37 4.1 Introduction 37 4.2 Slow-Wave Meander Branch-Line Coupler Design 38 4.2.1 Design Method 38 4.2.2 The Simulation Results of Slow-Wave Meander Branch-Line Coupler with Differential Pads 40 4.2.3 The Measured Results of Slow-Wave Meander Branch-Line Coupler 42 4.3 Discussion and Conclusion 45 Chapter 5 77 GHz EC-CPW Wilkinson Power Divider with Slow-Wave Structure 47 5.1 Introduction 47 5.2 EC-CPW Slow-Wave Wilkinson Power Divider Design 49 5.2.1 Wilkinson Power Divider 49 5.2.2 Slow-Wave Structure with EC-CPW 51 5.2.3 Design EC-CPW Wilkinson Power Divider with Slow-Wave Structure 52 5.2.4 The Simulation Results of EC-CPW Wilkinson Power Divider with Slow-Wave Structure 54 5.2.5 The Measurement Results of EC-CPW Wilkinson Power Divider with Slow-Wave Structure 57 5.3 Discussion and Conclusion 61 Chapter 6 Conclusion and Future Work 63 References 65

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