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研究生：	薛弘旻 Hsueh, Hung-Min
論文名稱：	以TCAD研究極化工程之氮化銦鎵p通道與鐵電氮化鋁鈧閘極堆疊之n通道高電子遷移率電晶體 TCAD Study of Polarization-Engineered InGaN p-Channel and Ferroelectric AlScN Gate Stack n-Channel HEMTs
指導教授：	王永和 Wang, Yeong-Her
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 奈米積體電路工程碩士博士學位學程 MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年：	2026
畢業學年度：	114
語文別：	英文
論文頁數：	163
中文關鍵詞：	高電子遷移率電晶體、氮化鋁鈧、氮化銦鎵、鐵電、TCAD
外文關鍵詞：	HEMT, AlScN, InGaN, Ferroelectric materials, TCAD
相關次數：	點閱：69 下載：2
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為建構多功能氮化鎵 (GaN) 平台之關鍵構成元件，本研究使用 Sentaurus TCAD 進行 p 型與 n 型高電子遷移率電晶體 (HEMT) 之設計與分析，旨在開發 CMOS 邏輯所需之 p 型元件，並探討兼具 E-mode 操作與非揮發性記憶體功能之 n 通道元件。
針對 p 型元件，本研究提出 InGaN/AlGaN 異質結構，利用極化效應誘發二維電洞氣 (2DHG)。經由系統性參數與尺寸縮放分析，最終共最佳化元件 (Lg = 0.5 μm, Lsd = 0.5 μm) 達成 E-mode 操作 (Vth = - 0.16 V)，具備 63.78 mV/dec 之次臨界擺幅、116 mA/mm 之導通電流、超過 1010 之開關電流比，及 6.2 mV/V 之低 DIBL。
針對n型元件，則導入鐵電氮化鋁鈧 (AlScN) 閘極堆疊結構。藉由結合 Ginzburg-Landau-Khalatnikov (GLK) 方程式與 TCAD 解析微觀極化切換機制，證實元件具備常開/常關切換特性，並達成臨界電壓(Vth) 為 0.72 V 之常關型操作。此外，進一步探討 AlScN/Al2O3/AlGaN/GaN 變體結構，證實了由介面陷阱主導的第二種 E-mode 實現途徑。此外，AlScN 鐵電閘極堆疊之可程式化臨界電壓與非揮發性極化特性，使該元件亦適合作為氮化鎵平台上的非揮發性記憶體應用。
本研究建立之參數設計空間，為未來開發氮化鎵 CMOS 邏輯與非揮發性記憶體應用提供了理論基礎與元件設計參考。

To develop key building blocks for the multi-functional Gallium Nitride (GaN) platform, this study investigates the design and characteristics of p-channel and n-channel high-electron-mobility transistors (HEMTs) using Sentaurus TCAD, aiming to develop a p-channel device for CMOS logic applications and to explore an n-channel device that enables both enhancement-mode (E-mode) operation and non-volatile memory functionality.
For p-type devices, an InGaN/AlGaN heterostructure is proposed to induce a two-dimensional hole gas (2DHG) via polarization effects. Through systematic parametric and dimensional scaling analyses, the co-optimized device (Lg = Lsd = 0.5 μm) achieves E-mode operation (Vth = -0.16 V) with near-thermionic SS (63.78 mV/dec), Ion = 116 mA/mm, Ion/Ioff > 1010, and DIBL = 6.2 mV/V.
For n-type devices, a ferroelectric AlScN gate stack is integrated. Leveraging the GLK equation and TCAD, the microscopic polarization switching mechanisms are analyzed, demonstrating D/E-mode switching and achieving E-mode operation with Vth = 0.72 V. Additionally, an AlScN/Al2O3 variant is investigated, revealing a second, interface-trap-driven E-mode pathway characterized by an opposite Vth–Vpoling polarity. Furthermore, the programmable Vth and non-volatile polarization retention of the AlScN gate stack make it a promising candidate for non-volatile memory applications on the GaN platform.
The parametric design space established in this work provides a robust theoretical foundation for future GaN CMOS logic and non-volatile memory applications.

摘要								 	                                                            I
Abstract						     	 	                                                          III
誌謝									                                                           V
Contents						      		                                                         VII
List of Figures								                                                  XI
List of Tables						     	                                                      XVII
Chapter 1	Introduction						                                                    1
1	Background							                                                            1
2	Motivation						 	                                                            4
3	Introduction of Synopsys Sentaurus TCAD		       		                            6
3.1	SDE								                                                            7
3.2	SPROCESS							                                                    7
3.3	SDEVICE							 	                                            7
3.4	SVISUAL								                                            8
Chapter 2	Simulation Methodology and Physical Theory		                    9
1	Device Structure					 	                                                            9
1.1	n-Channel HEMT with AlScN Gate Stack				                    9
1.2	n-Channel HEMT with AlScN/Al2O3 Bilayer Gate Stack		          10
1.3	InGaN/AlGaN p-Channel HEMT					                          11
2	Key Physical Mechanisms						                                          12
2.1	Polarization Effects						                                          12
2.2	Formation of 2DEG and 2DHG					                          16
2.3	Ferroelectricity in AlScN					                                          21
3	TCAD Physical Models						                                          25
3.1	Fermi-Dirac Statistics						                                          26
3.2	Mobility Model							                                          28
3.3	Recombination Model						                                  30
3.4	Polarization Model						                                          32
3.5	Ferroelectric Model						                                          34
3.6	Trap Model							                                                  35
4	Model Calibration						                                                  38
4.1	n-Channel AlScN Gate Stack HEMT Calibration			                  38
4.2	p-Channel InGaN/AlGaN p-FET Calibration				          41
5	Electrical Parameter Extraction Methods				                          42
5.1	Threshold Voltage						                                          43
5.2	Subthreshold Swing						                                          44
5.3	On-Resistance							                                          44
5.4	Ion & Ioff							                                                  46
5.5	Transconductance						                                          47
5.6	Drain-Induced Barrier Lowering					                          48
Chapter 3	Results & Discussion					                                          49
1	Chapter Overview						                                                  49
2	InGaN/AlGaN p-Channel HEMT					                                  49
2.1	Long-Channel Reference Device					                          49
2.2	Parametric Study					                                                  54
2.3	Summary of Parametric Study					                          90
2.4	Gate Length Scaling						                                          92
2.5	Access Length Scaling						                                  97
2.6	Co-Optimized E-Mode Device					                        103
3	n-Channel HEMT with AlScN Gate Stack				                        107
3.1	Polarization-Driven Vth Modulation (AlScN Gate Stack)		        108
3.2	Polarization-Induced Trap Charging (AlScN/Al2O3 Gate Stack)	124
Chapter 4	Conclusions						                                                132
1	InGaN/AlGaN p-Channel HEMT					                                132
2	AlScN Gate Stack n-Channel HEMT					                        134
Chapter 5	Future Works						                                        137
1	Experimental Validation of the p-HEMT				                        137
2	AlScN Ferroelectric Reliability Assessment			                                137
3	AlScN/Al2O3/AlGaN/GaN Structure					                        138
4	GaN CMOS Integration						                                        138
5	GaN Memory Circuit Integration					                                139
Chapter 6	References						                                                140
                                    

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