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| 研究生： |
黃喬楷 Huang, Ciao-Kai |
|---|---|
| 論文名稱： |
平行多核處理器架構之研究與實現 Analysis and Implementation of Parallel Multi-core Architectures |
| 指導教授： |
周哲民
Jou, Jer-Min |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年： | 2016 |
| 畢業學年度： | 104 |
| 語文別： | 中文 |
| 論文頁數： | 83 |
| 中文關鍵詞： | 多核處理器架構 、控制處理器 、亂序執行處理器 |
| 外文關鍵詞： | MLCA, GEM5, O3CPU |
| 相關次數： | 點閱：166 下載：8 |
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本論文主要針對平行多核處理器架構研究，首先分析由SystemVerilog所建立的多層級計算架構(Multi-Level Computing Architecture ,MLCA)，深入了解上層任務層級平行的控制處理器(Control Processor,CP)執行行為後，設計下層處理器單元(Processing Unit, PU)與周邊記憶體，實現MLCA平行多核架構； MLCA上層CP負責在執行時分析及記錄任務之間的相依關係，將就緒的任務分配給底層PUs平行執行並將執行結果回傳給CP記錄。
接著了解以C++及Python語言撰寫而成的 GEM5模擬器的模擬系統配置方式，根據使用者的需求快速、精確且高彈性地模擬出目標平台，本論文研究了指令層級平行的ARM亂序執行處理器(out-of-order CPU,O3CPU)的執行行為並透過GEM5模擬器實現具L1、L2快取階層的ARM O3CPU多處理器架構。
在不同平行多核處理器架構下測試不同的多執行緒測試程式與多任務測試程式，由程式的指令組成來分析在整個系統中發生效能瓶頸可能的原因，並針對問題點做對應的敏感資源配置調整達到執行程式的優化；
最後比較指令層級處理器/任務層級處理器差異、比較執行緒層級GEM5多處理器架構/MLCA任務層級多處理器架構間的差異。
In this thesis, we study and analysis of multi-processor architecture for various parallel multi-core architecture.
Firstly, we study and analysis task level control processor hardware architecture and its behavior to design the underlying processor units(PUs) and peripheral memory for implementation of multi-level computing architecture(MLCA) which established by the SystemVerilog. The control processor keeps tacking dependencies between tasks, automatically extracts parallelism among coarse-grain tasks and schedules them for execution on underlying processors.
And then, we implement ARM O3CPU mulit-processor architecture with L1, L2 caches by using gem5 simulator which is a cycle accurate simulator simulates pipeline stages cycle by cycle, we can configure and simulate the target platform as soon as possible.
We have made a comparison between ARM O3CPU mulit-core architecture and MLCA with various multi-thread/multi-task testbenchs.
[1] Chuck Moore, "DATA PROCESSING IN EXASCALE-CLASS COMPUTER SYSTEMS", The Salishan Conference on High Speed Computing, 2011.
[2] Hammond, L., Hubbert, B., Siu, M., Prabhu, M. K., Chen, M., & Olukolun, K. "The Stanford hydra cmp". Micro, IEEE, 20(2), 71-84, 2000.
[3] Karim, F., Mellan, A., Nguyen, A., Aydonat, U., & Abdelrahman, T. "A multilevel computing architecture for embedded multimedia applications". Micro, IEEE, 24(3), 56-66, 2004.
[4] Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., Saidi, A., Basu, A., & Wood, D. A. "The GEM5 simulator". ACM SIGARCH Computer Architecture News, 39(2), 1-7, 2011.
[5] Binkert, N. L., Dreslinski, R. G., Hsu, L. R., Lim, K. T., Saidi, A. G., & Reinhardt, S. K. "The M5 simulator: Modeling networked systems". IEEE Micro, (4), 52-60, 2006.
[6] Martin, Milo MK, et al. "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset." ACM SIGARCH Computer Architecture News 33.4, 2005.
[7] Stephen A. Edwards "Verilog 1995, 2001, and SystemVerilog 3.1 Languages for Embedded Systems",2004.
[8] C++ programming language. http://www.cprogramming.com/
[9] The official home of the Python Programming Language. https://www.python.org/
[10] Capalija, D., & Abdelrahman, T. S. "Microarchitecture of a coarse-grain out-of-order superscalar processor". Parallel and Distributed Systems, IEEE Transactions on, 24(2), 392-405, 2013.
[11] Control processor : http://www.eecg.toronto.edu/~davor/MLCA/
[12] SimObject : http://www.gem5.org/docs/html/classSimObject.html
[13] ISA Support Matrices: http://www.m5sim.org/Status_Matrix.
[14] Simplified Wrapper and Interface Generator : http://www.swig.org/
校內：2020-09-01公開校外：2020-09-01公開