語音與音訊信號處理技術被廣泛的應用在許多消費性產品當中，其硬體規格針對不同的使用層面也有些許不同。針對這些使用範疇，採用定點運算進行開發的演算法，應用於無浮點運算單元(Floating-Point Unit)的低階嵌入式開發環境，相較於浮點運算而言，能有效提升處理效能並降低開發成本。除此之外，以定點運算為基礎的硬體設計更能進一步減少其晶片面積及功耗。在此，本論文主要針對語音與音訊處理上運算量較高的部份進行演算法與硬體之優化，分為以下三個部份。
在第一部份，本論文將對語音壓縮中經常使用的線頻譜對 (Line Spectral Pairs) 運算，進行演算法與其硬體設計上之改良。針對不同階數的線頻譜對，提出了一個基於協同式運算的硬體架構。此協同式運算主要包含了伯奇-韋達法 (Birge-Vieta method) 與改良式契爾豪森轉換 (Enhanced Tschirnhaus Transform)。在本部份，本工作分析了伯奇-韋達法的係數相依性，並在中，減少了原算式中大量的小數運算，提出了一個基於整數運算的改良式契爾豪森轉換，來降低運算複雜度，使得大多數的乘法與除法運算得以使用位移及加法來替代。在實驗結果中，在相同的操作頻率上，所提出的硬體架構能有效的提升約40 倍的處理速度，並減少約1.16%的邏輯閘數量。
在第二部份，本論文提出了一個低複雜度的音訊編解碼器，應用於無浮點運算器之低階嵌入式系統。為了降低運算量運算與系統資源的消耗，提出的編解碼器僅使用了處理器中包含的基本的整數運算，以避免在一般音訊編碼器中經常使用到的複雜數學函式。在此編碼器中，主要包含了一個三種狀態的編碼模式，並使用了對應的資料型態標記轉換頻率域後之零信號，以提升壓縮率。實驗的結果顯示，在低階嵌入式開發板上的表現，所提出的編碼器與解碼器，相較於其他編碼標準，在程式碼大小上減少了約95%以上，提升了約113 倍以上的速度，並提供了近似的音質。
在第三部份，本論文提出了一個基於提出了一個基於定點格式的演算法來實現來二變數的幂函数(Power Function)。相較於原始浮點數的版本，此函數能有效的提升在低階嵌入式開發板上。此外，考慮到語音處理上經常使用的運算及大量數學函式上的需求。在此研究背景下，來設計一個可重組式運算單元來計算在語音處理上經常使用的超越函式及設計來提升硬體之使用率。實驗結果顯示，我們所提出的演算法執行在無浮點運算器的低階嵌入式開發板中，和原浮點函式相比，達到約5 倍速度的提升。此外，我們所設計的硬體架構可操作在200MHz 的頻率下並僅有11.7K 的邏輯閘大小，此硬體應能有效的應付大部份的語音信號處理上的運算。

Speech signal processing has been widely used in many consumer products for various applications. These applications might use different hardware specifications for different user needs. In the selection of the digital numeral system, fixed-point arithmetic is more appropriate than floating-point arithmetic to be applied in low-end embedded system which usually have no floating point unit (FPU). The fixed-point arithmetic can effectively improve the processing efficiency and reduce development costs. Moreover, the fixed-point hardware design is more efficient to reduce their usage of gate count and power consumption. This dissertation focuses on the high-complexity computations of speech and audio processing and design their algorithms and hardware architectures to accelerate computational performance. Three different topics are discussed in this dissertation.
In the first part of this dissertation, this work proposes a low-complexity algorithm and the corresponding hardware design for solving line spectrum pairs (LSPs). The proposed algorithm includes two main parts, the enhanced Tschirnhaus transform (ETT) and the Birge-Vieta method (BVM). The ETT replaces the fractional multiplications by several additions and shift operations so the redundant multiplication in original transform can be avoided. Besides, by analyzing the coefficient correlation of the BVM, a pipeline-recursive framework is implemented to save more calculation. The experimental results reveal that the proposed ETT can reduce the computation about 70.1%. Moreover, at the same operating frequency, the proposed hardware architecture can effectively enhances the performance of about 40 times, and reduce the amount of logic gates around 1.16%.
In the second part of the dissertation, this work presents a fixed-point algorithm and its hardware architecture based on a reconfigurable scheme for common-used transcendental functions and basic operations for speech signal processing. By analyzing the adopted algorithms of the above operations, a simplified computing unit is designed. This unit combines six types of operation by reconfiguring the data paths, the same multiply-add architecture can be reused for reducing the usage of logic gates. The experimental results indicate that in algorithm level, the proposed one can enhance about 5-fold computational performance performed in low-end embedded system. Furthermore, the proposed hardware design also can work at 200MHz clock rate, with only 11.9K of gate count, the average errors of logarithm and powering function respectively are 0.57% and 0.11%.
The third part of this dissertation presents a low complexity audio coder and decoder (CODEC) for the low-end embedded system with no FPU. For reducing computational complexity and system resource consumption, the proposed CODEC only uses the basic fixed-point arithmetic instructions to avoid the high-complexity mathematical functions in the conventional audio CODEC. To further improve the compression rate, a tri-mode zeroes recording algorithm (TZRA) is proposed. The proposed algorithm utilizes different encoding modes with the corresponding bit data structures which can be effectively used to record the locations of zero wavelet coefficients, and determines the optimal encoding mode which has the fewest bits. Compared with the baseline CODECs, the experimental results show that the proposed CODECs can reduce the size of the binary file about 95%, and provides 113-fold computation speed. The proposed system still maintains the approximate sound quality.

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