「晶圓級封裝(Wafer-level packaging, WLP)」是一種半導體封裝技術，相較於傳統封裝工藝更為微小、薄型化且成本更低。在眾多的晶圓級封裝技術當中，「全模塑型扇出晶圓級封裝技術(Fully Molded Fan-Out Wafer Level Packaging)」已成為高端晶片封裝的主流技術，具有諸多優勢，例如較強的封裝強度、較佳的良率、更長久的可靠性、以及更小的翹曲現象。
然而，由於COVID-19大流行引起晶圓供需失衡，晶片短缺已成為全球性問題。為了減少晶圓和晶片的報廢數量，提高製程能力指標並增加製程良率至關重要。相比於8英寸晶圓，在12英寸晶圓上電鍍銅柱高度的製程能力指標無法達到同等基線，導致良率低於量產要求。
因此，本研究採用因果分析法來找出影響12吋晶圓表面電鍍銅柱高度的主要因素，再使用TRIZ理論的矛盾矩陣法，獲得改善和惡化的關鍵因素，並得出啟發式解決方案，以有效地提升電鍍銅柱高度的製程能力指標(超過1.67)，並實現製程良率的提高(無銅柱高度超過規格)，以達成大量生產目標。

Wafer-level packaging (WLP) is a semiconductor packaging technology that offers advantages over traditional packaging processes, including smaller size, greater thinness, and lower cost. Fully molded fan-out wafer-level packaging (FOWLP), among various types of WLP, has emerged as the mainstream high-end chip packaging technology due to its stronger package strength, improved yield, longer reliability, and smaller warpage.
However, the global shortage of chips resulting from the COVID-19 pandemic has created an imbalance between wafer supply and demand. To minimize wafer and chip wastage, it is crucial to increase process capability index and assembly yield. The 12-inch wafer fails to achieve the same process capability baseline for plated Cu stud height as the 8-inch wafer, leading to lower yield rates than mass production requirements.
Thus, this study employs cause-effect analysis to determine the primary fac-tors affecting Cu stud plating height through electroplating on the surface of 12-inch wafers. The TRIZ contradiction matrix method is utilized to identify key fac-tors for both improvement and deterioration and obtain innovative invention solu-tions to improve the process capability index of the plated Cu stud height (exceed-ing 1.67) and increase process yield (no Cu stud height exceeding specification) to achieve mass production targets.

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