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研究生：	徐祥哲 Hsu, Shaing-Jer
論文名稱：	運用多重擷取順序降低功率消耗之技術 Power Reduction with Multiple Capture Orders
指導教授：	李昆忠 Lee, Kuen-Jong
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2003
畢業學年度：	91
語文別：	英文
論文頁數：	50
中文關鍵詞：	降低功率消耗、測試
外文關鍵詞：	power reduction, testing
相關次數：	點閱：53 下載：1
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本論文提出一個新穎的方法來降低測試時過度的平均以及尖峰功率消耗。所提出的方法將一條掃描鍵切成多條次掃描鍵(sub-chains)，而且在掃描以及擷取週期時一次只驅動一條次掃描鍵。為了有效解決在擷取週期時所造成資料相依的問題，我們採用多重的擷取順序來保證全掃描的錯誤涵蓋率。此外一個創新的測試向量產生程序被發展出來降低測試執行時間，另外一個以環狀控制結構為基礎的測試架構也被提出，此測試架構可以使得測試控制變得很簡單而且所需要的額外硬體負擔也非常少。根據對ISCAS89電路實驗結果顯示，當我們將一條掃描鍵切割成八條次掃描鍵時，花費與原先幾乎相同的測試執行時間就可以平均地降低平均以及尖峰功率消耗到86.7%以及66.8%。

This thesis proposes a novel method to reduce the excess average and peak power dissipations during scan testing. The proposed method divides a scan chain into many sub-chains, and enables only one sub-chain at a time for both the scan and capture operations. To efficiently deal with the data dependence problem during the capture cycles, we adopt multiple capture orders to guarantee the full scan fault coverage. A novel test pattern generation procedure is developed to reduce the test application time and a test architecture based on a ring control structure is also presented which makes the test control very simple and requires very low area overhead. Experimental results for large ISCAS’89 benchmark circuits show that with about the same test application time as the conventional scan method, the proposed method can reduce average and peak power by 86.7% and 66.8% in average, respectively, when 8 sub-chains are used.

CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Motivation........................................................................................................ 1
2. Introduction to Proposed Multiple Capture Orders .................................... 2
3. Organization of Thesis ................................................................................... 3
CHAPTER 2 BACKGROUND AND PREVI OUS WORK . . . . . . . . . . . . . 6
1. Power Dissipation Model............................................................................... 6
2. Previous Work ................................................................................................. 7
CHAPTER 3 TEST STRATEGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1. Interleaving Scan and Capture ....................................................................10
2. Capture Violation Consideration.................................................................12
3. Multiple Capture Orders ..............................................................................13
C H A P T E R 4 TEST PATTERN GENERAT ION PROCEDURE . . . . . . 16
1. Capture Orders ..............................................................................................16
2. Test Pattern Generation Algorithm .............................................................18
2.1. Main Procedure .................................................................................19
2.2. Subroutine Greedy ............................................................................21
2.3. Subroutine BranchAndBound .........................................................23
3. An Example ...................................................................................................24
CHAPTER 5 TEST ARCHITECTURE AN D TEST APPLICA TION
CONTROL.........................................................................................30
1. Test Architecture ...........................................................................................30
2. Expansion for Multiple Scan Chains Design ............................................32
3. Test Application Control ..............................................................................33
CHAPTER 6 EXPERIMENTAL RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1. Test Application Time ..................................................................................41
2. Test Power Reduction...................................................................................43
3. Comparison....................................................................................................45
CHAPTER 7 CONCLUSIONS...................................................................................... 48
                                    

[1] L. Whetsel, “Addressable Test Ports – an Approach to Testing Embedded Cores,” In Proc. Int’l Test Conference, pages 1055-1064, 1999.

[2] S. Chakravarty, V.P. Dabholkar, “Two Techniques for Minimizing Power Dissipation in Scan Circuits During Test Application,” In Proc. Asian Test Symposium, pp. 24-329, 1994.

[3] M.S. Hsiao, “Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits,” In Proc. European Design and Test Conference, pp. 175-179, 1999.

[4] J. Rajski, J. Tyszer, “Arithmetic Built-In Self-Test for Embedded Systems,” Prentice Hall PTR, 1998.

[5] P. Girard, “Low Power Testing of VLSI Circuits: Problems and Solutions,” In Proc. Int’l Symp. on Quality Electronic Design, pp. 173-179, 2000.

[6] S. Wang, S.K. Gupta, “DS-LFSR: A New BIST TPG for Low Heat Dissipation,” In Proc. Intl. Test Conference, pp. 848-857, 1997.

[7] M. Abramovici, M.A. Breuer, and A.D. Friedman, “Digital System Testing and Testable Design,” Computer Science Press, 1990.

[8] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,” In Proc. VLSI Test Symposium, pp. 4-9, 1993.

[9] M.L. Bushnell, V.D. Agrawal, “Essentials of Electronic Testing,” Kluwer Academic, 2000.

[10] S. Gerstendorfer, H-J Wunderlich, “Minimized Power Consumption for Scan-based BIST,” In Proc. Int’l. Test Conference, pp. 77-84, 1999.

[11] J. Hirase, M. Hamada, “The Effect of Fault Detection by IDDQ Measurement for COMS VLSIs,” In Proc. Asian Test Symposium, pp. 144-149, 1994.

[12] R.R. Fritzemeier, J.M. Soden, and R.K. Treece, “Increased CMOS IC Stuck-at Fault Coverage with Reduced IDDQ Sets,” In Proc. Int’l. Test Conference, pp. 427-434, 1990.

[13] B. Pouya, A. Crouch, “Optimization Trade-offs for Vector Volume and Test Power,” In Proc. Int’l. Test Conference, pp. 873-881, 2000.

[14] X. Zhang, K. Roy, “Peak Power Reduction in Low Power BIST,” In Proc. Int’l. Symposium on Quality Electronic Design, pp. 425-432, 2000.

[15] A. Macii, E. Macii, and M. Poncino, “ Reducing Peak Power Consumption of Combinational Test Sets,” In Proc. 32nd Asilomar Conference on Signals, Systems and Computers, pp. 1042-1046, 1998.

[16] X. Zhang, K. Roy, “Design and Synthesis of Low Power Weighted Random Pattern Generation Considering Peak Power Reduction,” In Proc. Int’l. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 148-156, 1999.

[17] F. Corno, M. Rebaudengo, M. Sonza Reorda, and M. Violante, “Transformation-based Peak Power Reduction for Test Sequences,” In IEEE Alessandro Volta Memorial Workshop on Low-power Design, pp. 78-83, 1999.

[18] T-C. Huang, and K-J. Lee, “Reduction of Power Consumption in Scan-based Circuits during Test Application by an Input Control Technique,” IEEE Trans. on Computer-Aided Design, vol. 20, No. 7, pp. 911-917, 2001.

[19] Y. Bonhomme, P. Girard, C. Landrault, S. Pravossoudovitch, “Power Driven Chaining of Flip-Flops in Scan Architecture,” In Proc. Int’l. Test Conference, pp. 796-803, 2002.

[20] P. Girard, L. Guiller, C. Landrault and S. Pravossoudovitch, “A Test Vector Inhibiting Technique for Low Energy BIST Design,” In Proc. VLSI Test Symposium, pp. 407-412, 1999.

[21] V. Dabholkar, S. Chakravarty, I. Pomeranz and S.M. Reddy, “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application,” IEEE Trans. on Computer-Aided Design, vol. 17, No. 12, pp. 1325-1333, 1998.

[22] P. Girard, C. Landrault, S. Pravossoudovitch, and D. Severac, “Reduction of power consumption during test application by test vector ordering,” Electronics Letters, vol. 33, no. 21, pp. 1752-1754, 1997.

[23] S. Wang, and S.K. Gupta, “LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation,” In Proc. Int’l. Test Conference, pp 85-94, 1999.

[24] R. Sankaralingam, R.R. Oruganti, and N.A. Touba, “Static Compaction Techniques to Control Scan Vector Power Dissipation,” In Proc. VLSI Test Symposium, pp. 35-40, 2000.

[25] R. Sankaralingam, B. Pouya, and N.A. Touba, “Reducing Power Dissipation During Test Using Scan Chain Disable,” In Proc. VLSI Test Symposium, pp. 319-324, 2001.

[26] R. Sankaralingam, N.A. Touba, “Inserting Test Points to Control Peak Power During Scan Testing,” In Proc. Int’l Symposium on Defect and Fault Tolerance in VLSI System, pp. 138-146, 2002.

[27] R. Sankaralingam, N.A. Touba, “Controlling Peak Power During Scan Testing,” In Proc. VLSI Test Symposium, pp. 153-159, 2002.

[28] F. Corno, M. Rebaudengo, M. Sonza Reorda, and M. Violante, “On Reducing the Peak Power Consumption of Test Sequences,” In Proc. European Conference on Circuit Theory and Design, pp. 247-250, 1999.

[29] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, “Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption,” In Proc. Asian Test Symp., pp. 89-94, 1999.

[30] K-J. Lee, T-C. Huang, and J-J. Chen, “Peak Power Reduction for Multiple-Scan Circuits during Test Application,” In Proc. Asian Test Symp., pp. 453-458, 2000.

[31] N. Weste, and K. Eshraghian, “Principles of CMOS VLSI Design,” Addison Wesley, Mass., 1993.

[32] F.N. Najm, “A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE Trans. on VLSI Systems, pp. 446-455, 1994.

[33] F.N. Najm, “Transition Desity: A New Measure of Activity in Digital Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 310-323, 1993.

[34] H. Ueda and K. Kinoshita, “Low power design and its testability,” In Proc. Asian Test Symp., pp. 361-366, 1995.

[35] K.I. Diamantaras and N.K. Jha, “A New Transition Count Method for Testing of Logic Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 407-410, Mar. 1991.

[36] Lee Whetsel, “Adapting scan architectures for low power operation,” In Proc. Int’l. Test Conference, pp. 863-872, 2000.

[37] P.M. Rosinger, B.M. Al-Hashimi, and N. Nicolici, “Scan Architecture for Shift and Capture Cycle Power Reduction,” In Proc. Int’l Symposium on Defect and Fault Tolerance in VLSI System, pp. 129-137, 2002.

[38] T.H. Cormen, C.E. Leiserson, R.L. Rivest, and C. Stein, “Introduction to Algorithms,” McGraw-Hill, 2001.

校內：2018-07-04公開
校外：2018-07-04公開

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