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研究生： 胡桓睿
Hu, Huan-Jui
論文名稱： 一個時序偏移不敏感之十位元每秒取樣六億次雙通道逐漸趨近式類比數位轉換器
A 10-bit 600-MS/s 2x-Interleaved Timing-Skew Insensitive Successive-Approximation Analog-to-Digital Converter
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2019
畢業學年度： 107
語文別： 英文
論文頁數： 134
中文關鍵詞： 類比數位轉換器 、逐漸趨近式 、時間交錯式 、子範圍 、循環展開 、時序偏移
外文關鍵詞： analog-to-digital converter (ADC), successive-approximation register (SAR), time-interleaved (TI), sub-range, loop-unrolled, timing-skew
相關次數： 點閱：125  下載：22 
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    • 本論文提出一個不敏感於時序偏移的10位元每秒取樣六億次的雙通道逐漸趨近式類比數位轉換器。透過結合子範圍架構(Sub-range)和多比較器架構(Multi-comparator)來實做出操作在高速的子通道，並且兩者架構所產生出來的錯誤量可以透過調整冗餘演算法(Redundancy Algorithm)來容忍。憑藉所提出的高速子通道架構，每秒取樣六億次的規格僅需要兩個子通道即能達成，至於雙通道間的時序偏移(Timing-skew)則利用本論文所改良的取樣與保持電路(Track-and-Hold Circuit)盡可能地減少，因此本架構並不需要使用任何代價高昂的時序偏移校正引擎(Calibration Engine)。
    本設計以台積電40奈米CMOS製程實作測試晶片，其核心電路面積佔0.0963mm2。當晶片操作在輸入電壓1.1伏特與取樣速度六億次時，測試結果顯示本晶片在低輸入頻率下能夠達到56.98 dB的失真比(SNDR)，而在奈奎斯特(Nyquist-rate)輸入頻率下，可以達到46.6 dB的失真比，其換算得到的轉換效率分別為21.2 fJ/conversion-step及68.5 fJ/conversion-step。因時序偏移所產生出的錯誤在奈奎斯特輸入頻率下約為 -75.03dB，其所估計的雙通道間時序偏移小至94 fs。

    This thesis presents a 10-bit 600-MS/s 2-way interleaved successive-approximation register (SAR) analog-to-digital converter (ADC) which is insensitive to the timing-skew. The sub-range and multi-comparator architecture are adopted to implement the high speed sub-channel and the errors induced from this configuration are tolerated by manipulating the redundancy algorithm. Thanks to the high speed sub-channel, the sampling rate of 600-MS/s is achieved with merely two channels and the effect of timing-skew is well mitigated with the modified Track-and-Hold Circuit. Hence, the costly timing-skew calibration engine is no longer required in this work.
    The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology, of which the core circuits cover an area of 0.0963mm2. As the prototype operates at a supply voltage of 1.1-V and sampling rate of 600-MS/s, the measurement result shows the prototype achieves 56.98 dB SNDR with low input frequency and 46.6 dB SNDR with input frequency up to Nyquist-rate. Accordingly, the Figure of Merit (FoM) are 21.2 fJ/conversion-step and 68.5 fJ/conversion-step, respectively. The tone induced by timing-skew error is -75.03 dB with a Nyquist-rate input, for which the timing-skew between sub-channels is estimated to be as low as 94 fs.

    摘 要 III Abstract IV List of Tables X List of Figures XI Chapter 1 Introduction 1 1.1 Background 1 1.2 Time-interleaved ADC 4 1.3 Organization 6 Chapter 2 High-speed SAR ADC 7 2.1 The Basics of SAR ADCs 7 2.2 Speed Limitation 9 2.2.1 Comparison Time 11 2.2.2 Comparator Reset Time 14 2.2.3 DAC Settling Time 15 2.2.4 Logic Delay 17 2.3 Techniques of Speed Enhancement 19 2.3.1 Asynchronous Timing Control 19 2.3.2 Control Logic Design 22 2.3.3 Sub-range Architecture 26 2.3.4 Multi-comparator Architecture 31 2.3.5 Non-binary Algorithm 33 Chapter 3 Time-interleaved ADC 40 3.1 Analysis of Time-interleaved ADCs 41 3.1.1 Sampling in Time and Frequency Domain 41 3.1.2 Mismatches between Channels 48 3.1.3 The Effect of Channel Errors 49 3.2 Techniques to Mitigate The Offset and Gain Error 57 3.2.1 Offset Calibration 59 3.2.2 Gain Calibration 60 3.3 Methods to Alleviate Timing-skew Error 61 3.3.1 Two-Rank Track-and-Hold 61 3.3.2 Timing-skew Calibration 63 3.3.3 Global Clock Technique 74 Chapter 4 A 10-bit 600-MS/s 2x-interleaved Timing-skew insensitive SAR ADC 77 4.1 Introduction 77 4.2 Proposed Architecture 79 4.2.1 Hybrid SAR ADC with Loop-unrolled Technique 79 4.2.2 Timing-skew Insensitive Track-and-Hold Circuit 82 4.3 Design Consideration 86 4.3.1 Switching Methods 86 4.3.2 Required Error Tolerance Range 88 4.4 Circuit Implementation 91 4.4.1 Bootstrapped Switch 91 4.4.2 Dynamic Comparators 93 4.4.3 Phase Generator 96 4.4.4 Digital Control Logic Circuits 97 4.4.5 Capacitive DAC 101 Chapter 5 Simulation and Measurement Results 104 5.1 Layout and Chip Floor Plan 104 5.2 Simulation Results 107 5.3 Die Micrograph and Measurement Setup 111 5.4 Measurement Results 115 Chapter 6 Conclusion and Future Works 122 Bibliography 126  

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