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研究生：	林宗翰 Lin, Tsung-Han
論文名稱：	電阻式記憶體變異性之簡單模型及其對類神經電路之影響 Compact Modeling of Variability in RRAM Devices and its Impact on Neuromorphic Circuit Applications
指導教授：	盧達生 Lu, Darsen
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2018
畢業學年度：	106
語文別：	英文
論文頁數：	52
中文關鍵詞：	電阻式記憶體、類神經網路、蒙地卡羅
外文關鍵詞：	RRAM, Neural Network, Monte Carlo
相關次數：	點閱：129 下載：27
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近年來，電阻式記憶體(RRAM)被廣泛研究，許多應用都使用電阻式記憶體作為當中的元件，而類神經網路為其中之一，因電阻式記憶體的結構簡單與成本較低，使電阻式記憶體可作為類神經網路中的神經單元應用；此外因電阻式記憶體的特性，使其電阻的阻值可被調變，可做為類神經網路中的權重選擇。
本研究為了探討電阻式記憶體的不穩定性，會使調變後的電阻對於理想值會有差異性，同時將電阻式記憶體應用於邏輯閘電路中，觀察RRAM阻值的不穩定性對於邏輯閘電路之影響，電阻式記憶體的資料萃取於本實驗室所製成的元件，再利用Hspice model模擬與參數萃取來得到RRAM的電流電壓曲線，並使用蒙地卡羅數值模擬的方式，模擬出RRAM電阻的變異性，最後將蒙地卡羅模擬與邏輯閘電路結合，以達到實驗結果。

In the recent years, Resistance Random Access Memory has been widely studied. RRAM devices can be employed in many applications, among which neural networks is one. Because the structure of a RRAM device is simple and inexpensive, RRAM can be used as the neural cells in a neural network. In addition, due to the characteristics of RRAM devices, the resistance can be modified as the weight in the neural network.
In order to investigate resistance instability in a RRAM device, the resistance after modulation will be different from that of the ideal value. Therefore, a logic gate circuit using a RRAM device is designed in order to observe the effects on resistance variability for the logic gate current. The RRAM device is fabricated in our lab, and the I-V curve is simulated using the HSPICE model. In addition, the Monte Carlo method is used in the model to simulate the resistance variability of the RRAM device.
Finally, the Monte Carlo simulation and logic gate circuit are combined to achieve the results of the experiment.

Content
摘要	i
Abstract	ii
Acknowledgement	iv
Content	v
Figure captions	viii
Table captions	xi
Chapter 1	1
Introduction	1
1.1	Storage Class Memory	1
1.1.1	NAND Flash memory	1
1.1.2	Magnetoresistive RAM, MRAM	2
1.1.3	Phase Change Memory, PCRAM	3
1.1.4 Resistive Radom Access Memory, RRAM	4
1.2	Research motivation	5
Chapter 2	6
Background theory	6
2.1 Conduction mechanisms	6
2.1.1	Schottky emission	6
2.1.2	Fowler-Nordheim (F-N) and direct tunneling	7
2.1.3	Poole-Frenkel (P-F) emission	9
2.1.4	Space charge limited conduction (SCLS)	10
2.1.5	Ionic conduction	10
2.1.6	Ohmic conduction	10
2.1.7	Nearest-neighbor hopping (NNH)	11
2.1.8	Mott variable-range hopping (VRH)	12
2.1.9	Trap-assisted tunneling (TAT)	13
2.2 Resistive switch mechanisms	14
2.2.1 Filament mechanism	14
2.2.2 RRAM parameters	16
2.3 The HSPICE model	17
2.4 Monte Carlo Simulation	18
Chapter 3	19
Introduction to HSPICE setting	19
3.1 Current Calculation Module	20
3.1.1 Drift velocity	20
3.1.2 LRS calculation	22
3.1.3 Reset process	23
3.2 Memory Module	25
Chapter 4	26
Research Results and Discussion	26
4.1 Simulated RRAM Device	26
4.1.1 RRAM Device Structure	26
4.1.1 Experimental data for RRAM	28
4.2 Parameter Extraction	32
4.3 Monte Carlo simulation	34
4.4 Circuit Application	40
Chapter 5	49
Conclusion	49
References	50






 
Figure captions
Fig. 1-1 The cross-section schematic of a flash cell	2
Fig. 1-2 A cross-section schematic of a MRAM	3
Fig. 1-3 A cross-section schematic of the conventional PCRAM	4
Fig. 1-4 The cross-section schematic of the RRAM cell	5
Fig. 2-1 Schematic energy band diagram of Schottky emission	7
Fig. 2-2 Schematic energy band diagram of Fowler-Nordheim tunneling	8
Fig. 2-3 Schematic energy band diagram of direct tunneling	8
Fig. 2-4 Schematic energy band diagram of the Poole-Frenkel emission	9
Fig. 2-5 Schematic energy band diagram of ohmic conduction	11
Fig. 2-6 Energy band diagram of hopping conduction	12
Fig. 2-7 Energy band diagram of nearest-neighbor hopping (NNH) and energy band diagram of variable-range hopping (VRH)	13
Fig. 2-8 Schematic filamentary conducting path model	15
Fig. 2-9 Schematic diagram of the electrochemical metallization mechanism	15
Fig. 2-10 Schematic diagram of the valance charge mechanism	16
 
Fig. 2-11 (a) Schematic of the MIM structure RRAM, and the (b) unipolar and (c) bipolar characteristics	17
Fig. 3-1 Schematic block diagram of the three	19
Fig. 3-2 The dependence of the RESET time on the RESET voltage; inset is dc reset voltage and target resistance	23
Fig. 3-3 Schematic of the RC circuit model	24
Fig. 4-1 Schematic diagram of the RRAM structure	28
Fig. 4-2 Schematic I-V curve for the HfO2-based and TiO2-based materials	30
Fig. 4-3 The photomask pattern of the RRAM device	31
Fig. 4-4 schematic the simple module of the compliance current	32
Fig. 4-5 Parameter extraction of the HfO2-based RRAM device	33
Fig. 4-6 Parameter extraction of the TiO2-based RRAM device	33
Fig. 4-7 Schematic the current distribution of the LRS and HRS	34
Fig. 4-8 Monte Carlo analysis flow in HSPICE	35
Fig. 4-9 Schematic current distribution of the experimental data and simulation data	37
Fig. 4-10 Discontinuous schematic I-V curve	38
Fig. 4-11 After modification, the current distribution of the experimental data and simulation data	38
Fig. 4-12 Schematic the circuit of 1T1R	40
Fig. 4-13 Schematic diagram of the wave form from input	41
Fig. 4-14 Schematic diagram of the current corresponding to different training Gate voltages	41
Fig. 4-15 The application circuit of the “AND GATE,” where parameter G is the training gate voltage; parameter T is the transistor, and parameter R is the RRAM resistance	43
Fig. 4-16 Schematic simulation results from HSPICE	45


 
Table captions
Table 4-1 Current distribution parameters of the simulation data	37
Table 4-2 After modification, current distribution parameters of the simulation data	39
Table 4-3 The truth table of “AND GATE”	42
Table 4-4 Parameters of the Gate Voltage used in the simulation	44
Table 4-5 Parameters of the input signal used in the simulation	44
Table 4-6 Schematic of the parameters for the AND GATE circuit	45
Table 4-7 Current distribution of RRAM applied on the AND GATE circuit	46
                                    

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校內：2020-08-19公開
校外：2020-08-19公開

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