現有的半導體製程技術或架構在摩爾定律的發展逼近物理極限的情形下已面臨許多瓶頸。有鑒於此，本論文旨在研究新製程架構的半導體製程技術。與以往使用CVD磊晶製作SiGe核殼電晶體的方法不同，本研究使用的是利用高真空濺鍍法生成Ge薄膜搭配熱擴散製程結合Si與Ge，生成SiGe合金，並透過化學蝕刻法製程去除殘存的Ge，成功的製作出多晶Si/SiGe核殼無接面聚集型場效電晶體。其中Si內核的高度為30奈米，SiGe殼層薄膜的厚度約為2nm。
在元件製作完成後，我們從不同的通道寬度與閘極長度切入，廣泛地討論了多晶Si/SiGe殼層無接面聚集型場效電晶體的電性。本研究製作SiGe薄膜的熱擴散製程條件有三種，並分別生成三種不同比例的SiGe。其中，當退火條件為700度6小時的電性表現相較其他兩種條件較不理想，我們推測是Ge因為過高的熱預算重新析出而無法生成SiGe薄膜導致。我們選擇了無接面聚集型(junctionless accumulation mode)電晶體希望可以避免短通道效應，但在電性結果的表現上，仍然可以從VTH的偏移現象與嚴重的DIBL表現觀察到短通道效應。儘管如此，此新製程製作出的元件驅動電流與傳統平面場效電晶體相比仍有很好的表現。

There face many bottleneck for present semiconductor technology or development that builds on Moore’s Law although it approaches the limit of physics. In view of this, the main goal of this study is to develop new technology of semiconductor. Different from the past method, which is epitaxy with CVD instrument, of fabricating SiGe core-shell transistors, this study is through high vacuum sputter to producing Ge thin film and combine Si and Ge to match the SiGe alloy by thermal diffusion process. Furthermore, though chemical etching process to remove residual Ge achieve to product poly Si/SiGe core-shell Juctionless accumulation mode (JAM) FinFET. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm.
After finishing the fabrication of devices, we widely study the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. The thermal diffusion process condition for this study are three and for fabricating three different content of Ge for each. We surmise that, among them, the annealing condition at 700℃ for 6 hours shows undesired electrical characteristics against the others result from over thermal budget cause a plenty of Ge to precipitate against to form SiGe thin film. We choose JAM transistors to hope to prevent short channel effect (SCE) but from the result of electric characteristics is still observed SCE with VTH offset phenomenon and severe Drain Induced Barrier Lowering (DIBL). Despite it, through this new process can still fabricate a comparable performance to classical planar FinFET in driving current.

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