由於半導體製造技術的進步，使得複雜的積體電路系統能夠順利地被實現。設計一個積體電路系統設計需要的時間及困難度大幅度地增加。為了簡化設計流程及縮短系統開發週期，創造高階描述語言及設計高階合成工具變成熱門的研究議題。高階合成是將在行為式描述層級的數位系統轉換成實際的硬體架構的過程。在高階合成的過程中，設計者應針對系統的能量及效能進行共同考量。可以藉由發展一些的演算法將系統的能量及效能在高階合程過程中納入考量。
本論文中，我們發展了一套設計自動化工具，主要是以SystemC描述的系統自動轉換成暫存器轉移階層Verilog。在轉換的過程中，我們加入一個啟發式的排程演算法，最小化系統的峰值功率。除此之外，藉由增加額外的控制邊緣的方法能夠有效地減少系統的能量消耗。
實驗結果顯示，系統的時間及資源限制納入考慮的前提下，針對數個測試範例，我們發展的工具，能夠有效地減少系統的峰值功率及能量，其中最大可節省的能量達到29%。

The advancement in semiconductor process technology has enabled a complex VLSI system to be fabricated. The time required and difficulty involved in designing such VLSI system has increased tremendously. The creation of high level description language and high level synthesis tool become a hot research topic for simplifying the design flow and shorten time to market. Trade-offs between energy and performance of the system is one of the important factors that designers need to decide.
In this thesis, a design automation tool that could translate SystemC to register-transfer level Verilog is developed. A heuristic scheduling algorithm is incorporated during the translation process to minimize the peak power of the system. Besides that, by using a method of control edge insertion could also reduce the energy consumption of the system.
Experiment results show that, under the time and resource constrains, the tool that developed in this thesis could effectively reduce the peak power and energy for some benchmark circuits and the maximum energy savings that could be achieved is about 29%.

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