數位電路的測試中，最被常使用到的測試技術之一是掃描測試技術。然而這項技術往往會面臨到過長的測試時間及過大的測試資料量這兩項最嚴重的問題。而上述的兩項問題將會造成對昂貴測試機台需求的增加。在本篇論文中，我們提出一個用於降低測試時間及測試資料量之掃描測試架構。本架構的基本觀念是在不增加額外的掃入接腳及掃出接腳的前提下去縮短掃描鍊的長度。從我們對 ISCAS-89 Benchmark 電路的實驗中可看出，此架構可同時達到極高的測試時間降低量及測試資料量降低量，特別是對大型的電路其降低量會更明顯。
我們同時也提出了一個新的無失真空間壓縮法 (space compression) 用以設計我們所提測試架構中的空間壓縮電路。此空間壓縮電路包含了 P1 及 P2 這兩塊疊接在一起的電路。P1 中包含了數個單一輸出之同位樹 (parity tree)，而 P2 中則是包含了一些邏輯閘。我們所提出的空間壓縮電路可將一個電路的大量輸出腳位壓縮到一個極小的數字。從我們對 ISCAS-85 Benchmark 電路的實驗可看出，若只使用 P1 的話，所有電路的輸出腳位均可被無失真壓縮到三至五個；而再使用 P2 的話，所有電路的輸出腳位均可再被無失真壓縮到只剩一個。而在對 ISCAS-89 Benchmark 電路的實驗中可看出，若只使用 P1 的話，所有電路的輸出腳位 (即代表該電路的原始輸出腳位及所有正反器之輸入腳) 均可被無失真壓縮到三至七個；而再使用 P2 的話，所有電路的輸出腳位均可再被無失真壓縮到最多兩個。

Scan-based techniques are the most commonly used design for test (DFT) techniques for large digital circuits. However, long test time and large amount of test volume are two serious problems in a scan-based design. The above two problems will result in more demand on the expensive automatic test equipment (ATE) which acts as the test sources and sinks during testing. In this thesis, we propose an advanced scan architecture for test time and test volume reductions. The basic idea of this architecture is to shorten the scan chain length without using extra scan-in or scan-out ports. Experimental results on ISCAS-89 benchmark circuits show that the proposed architecture can simultaneously achieve high test time reduction ratio (TTRR) and high test volume reduction ratio (TVRR), especially for large circuits.
We also propose a novel zero-aliasing space compression method for the advanced scan architecture. Our space compressor contains two cascade circuits, P1 and P2. The circuit P1 consists of a number of single-output parity trees, while P2 is composed of several types of logic gates. The proposed space compressor can compress a large number of outputs from a CUT into an extremely small number. Experimental results show that the outputs of all ISCAS-85 benchmark circuits can be compressed into three to five outputs by P1 and further compressed into exactly one output by P2, both without aliasing. As for ISCAS-89 benchmark circuits, the outputs, i.e., the primary outputs (POs) and flip-flops (FFs) input, can be compressed into three to seven outputs by P1 and at most two outputs by further using P2 with zero aliasing.

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