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研究生：	林璟汶 Lin, Ching-Wen
論文名稱：	作業系統管理的處理器與快取記憶體系統平台之在線式自我測試方案設計 An Effective On-Line Self-Testing Methodology for an OS-Managed Processor Core and Cache Platform
指導教授：	陳中和 Chen, Chung-Ho
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering
論文出版年：	2017
畢業學年度：	105
語文別：	英文
論文頁數：	83
中文關鍵詞：	軟體式自我測試、可測試性設計、動態電壓頻率調整、保護頻帶、電晶體老化效應
外文關鍵詞：	Design for testing (DFT), guardband, on-line testing, software-based self-test (SBST), transistor aging
相關次數：	點閱：140 下載：3
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軟體式自我測試對於處理器系統的製造測試是一種非常有效的方法。同時軟體式自我測試亦可以用來偵測處理器在晶片系統運作當中所產生的電路錯誤。本篇論文提出一套完整的系統架構層級方案，讓高錯誤涵蓋率的測試程式可以順利地執行在被作業系統所管理的處理器與快取記憶體系統上，並且不影響作業系統與其他程序的正常執行。這套方案我們稱為Processor Shield，其包括一套完整的軟體框架(software framework)與硬體可測試性設計(design for testing)。即便處理器系統發生錯誤而無法通過程式測試，本方案也具備保持作業系統不被毀損的能力。我們將所提出之方案實現在相容於ARMv5指令集的處理器上，並且將開發的測試程式執行於Linux作業系統之中。利用本方案執行的測試程式可以對於處理器核心與快取記憶體系統之測試涵蓋率達到99%以上。本方案之硬體成本為原處理器面積的0.494%，而測試程式執行在1GHz的處理器上均可以在8ms之內完成，其約相當於兩次上下文交換(context switch)之時間間隔。另外，我們也提出讓軟體式自我測試與動態電壓頻率調整(dynamic voltage and frequency scaling, DVFS)合作的機制。利用此機制可以動態校正所需要的最低保護頻帶(guardband)，以期得到更低的功率耗損並且減緩電晶體老化效應(transistor-aging effect)。

Software-based self-test (SBST) is an effective method to detect operational faults of a processor system. We propose an architectural approach to support high fault-coverage on-line SBST: Processor Shield, which tackles the difficult-to-test issues raised due to the protection of an operating system. The processor shield, including a software framework and design for testing (DFT) hardware, creates an on-line self-testing environment without influencing other processes and on-bus devices even if the SBST fails. We present a case study that demonstrates SBST executions under Linux kernel on an ARMv5-compatible processor system. For CPU testing, the stuck-at fault coverage is over 99% while the transition fault coverage is higher than 93%. For cache control logic testing, the stuck-at fault coverage is over 99% while the transition fault coverage is higher than 95%. For RAM module testing, the fault coverage is nearly 100%. Cache SBSTs finish in a context-switch interval of less than 4ms while CPU SBST finishes in less than 8ms for 1 GHz clock. The hardware overhead of the processor shield is only 0.494% of the whole processor area. We also present an SBST-DVFS application that calibrates the dynamic minimal guardbands and helps achieving lower power consumption and mitigating transistor-aging effect.

摘要	I
ABSTRACT	II
誌	 謝	III
TABLE OF CONTENTS	IV
LIST OF TABLES	VII
LIST OF FIGURES	VIII
CHAPTER 1	INTRODUCTION	1
1	MOTIVATION	1
2	INTRODUCTION TO THE PROPOSED METHOD	1
3	CONTRIBUTIONS	4
4	ORGANIZATION OF DISSERTATION	5
CHAPTER 2	BACKGROUND AND RELATED WORK	7
1	BACKGROUND KNOWLEDGE	7
2	RELATED WORK	8
3	OVERVIEW OF TARGET PROCESSOR	11
CHAPTER 3	ON-LINE SBST CHALLENGE FOR CPU AND CACHE 14
1	CHALLENGE FOR CPU CORE ON-LINE SBST	14
2	CHALLENGE FOR CACHE SYSTEM ON-LINE SBST	15
2.1	CACHE RAM CELL TESTING	15
2.2	CACHE CONTROLLER TESTING	16
CHAPTER 4	PROPOSED PROCESSOR SHIELD DESIGN 17
1	PROCESSOR SHIELD SOFTWARE FRAMEWORK	17
2	PROCESSOR SHIELD DFT HARDWARE	22
2.1	ADDRESS REDIRECTION FUNCTION FOR CPU TEST 23
2.2	ADDRESS REDIRECTION FUNCTION FOR CACHE TEST 24
2.3	EXTERNAL SIGNAL CONTROL	25
2.4	RESULT COMPRESSION	26
2.5	TIME-OUT COUNTER	27
2.6	FAULT EFFECT ISOLATION	28
2.7	DETAILED FUNCTION BLOCK	29
3	COMPARISON BETWEEN PROCESSOR SHIELD AND CONVENTIONAL SBST	30
4	SUMMARY	31
CHAPTER 5	PROCESSOR CORE ON-LINE SBST PROGRAM DEVELOPMENT	32
1	PROCESSOR CORE SBST BODY FUNCTION	32
2	SBST FAULT COVERAGE ENHANCEMENT	34
2.1	UNCOVERED FAULT FIRST RANDOM PROGRAM GENERATION 35
2.2	RTL CODING STYLE FOR SBST TESTABILITY	36
3	SUMMARY	39
CHAPTER 6	CACHE SYSTEM ON-LINE SBST PROGRAM DEVELOPMENT	41
1	CACHE TESTING CHALLENGES	41
2	TESTING-ORIENTED PAGE TABLE BUILDING	42
3	PSEUDO TESTING INSTRUCTIONS	45
4	DATA CACHE TESTING SEQUENCE	46
5	INSTRUCTION CACHE TESTING SEQUENCE	49
5.1	MARCH DATA BACKGROUND AND SBST PROGRAM	50
5.2	UNAMBIGUOUS INSTRUCTION CACHE TESTING	54
6	SUMMARY	56
CHAPTER 7	EXPERIMENTAL RESULTS	57
1	PROCESSOR CORE TEST RESULTS	59
2	CACHE RAM MODULE TEST RESULTS	60
3	CACHE CONTROL LOGIC TEST RESULTS	63
4	SBST SERVICE ROUTINE STATISTICS	64
5	PROCESSOR CORE FAULT COVERAGE ENHANCEMENT 67
6	SBST AND DVFS: REQUIRED GUARDBAND CALIBRATION 71
CHAPTER 8	CONCLUSION	74
REFERENCES	76
PUBLICATIONS	82
VITA	83
                                    

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