新一代導航衛星除了可以傳送L1頻段訊號外，也可傳送新一代L2以及L5頻段之訊號，若通訊導航接收機可採雙頻架構設計，則得以有效抑制電離層誤差、甚至多路徑效應。因此本篇論文在基於ZYNQ-7000的可程式系統晶片平台，來實作可以即時處理雙頻段的基頻訊號的處理器，透過軟體硬體共同設計的方法完成處理L1與L2雙頻段GNSS基頻訊號處理電路之架構，與透過可程式系統晶片(Programmable System On a Chip, PSoC)內部AXI匯流排架構與ARM處理器溝通，能夠以更小的面積、更低的功耗，獲得更加優異的性能，使用Free-RTOS作業系統進行演算法管理。同時本論文所發展接收機之架構顧慮到L2頻段訊號之電碼長度較長，在硬體資源有限之情況下，傳統訊號搜索方法會導致擷取訊號時間過長，使追蹤訊號之鎖相迴路脫鎖，因此於硬體上實際發展了雙頻快速訊號擷取演算法、透過設計平行處理架構降低擷取時間。在100 MHz的工作時脈下，ㄧ個具有L2頻段衛星訊號即時搜索的時間最慢縮短為36 ms，完成基於PSoC之雙頻即時GNSS接收機訊號接收架構，包含其硬體、軟體以及演算法實作。

The modernized GNSS satellites broadcast signals in three new frequencies to enhance the overall resistance to ionospheric and multipath error. In this research, a real-time dual-frequency GNSS receiver techniques are developed through the design and implementation of a PSoC based baseband signal processor. Through method of software and hardware codesign to complete L1 and L2 dual-frequency PSoC receiver architecture, The hardware communicates with ARM cortex-A9 through the internal AXI bus architecture. The signal processing algorithm is managed by Free-RTOS. Moreover, L1 based L2 signal acquisition embedded algorithms are design and implemented in PSoC receiver for L2 long code that will lead to failure of phase-locked loop. Through parallel processing DSP architecture. The signal of one satellite is stably captured less than 36ms under the 100MHz clock.

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