由於積體電路製程技術上的進步，系統單晶片 (System-on-a-chip, SoC)之設計方法逐漸成為積體電路設計之主流。在此嶄新且已被廣泛應用之觀念下，邏輯電路、處理器、記憶體、與類比電路等元件將會被整合在單一晶片中以大幅降低產品成本並縮短產品上市時間。然而此設計方法亦衍生出許多挑戰，其中最為複雜且極待解決的問題之一為單晶片系統之測試問題。
針對此項議題，我們已發展出一單晶片系統測試平台。此測試平台主要利用內嵌式處理器來控制整體系統單晶片之測試流程並有一功能強大之測試存取機制控制器來執行測試過程中所需之所有相關動作。另外針對此測試平台我們亦已分別發展一以軟體為主及以硬體為主之測試流程以達到高效能且具彈性之測試。基於此測試平台，在此篇論文中，我們致力於1)實現此測試平台於一以ARM處理器為基礎之系統發展板中以在實際情況下驗證此平台測試機制之正確性，2)將此平台之測試機制與待測電路分別實現在此系統發展板所提供之不同現場可程式化邏輯閘陣列(FPGA)中。利用此方式此測試平台之雛形(prototype)將可提供一系統單晶片發展環境。使用者僅需將矽智產電路實現在一FPGA中並與此系統整合即可輕易地驗證此電路不僅在一般模式下之行為並且還可更進一步地進行於測試模式操作下之驗證，為一相當創新且對使用者相當有益之特性，亦為本論文成果中最值得強調之貢獻之ㄧ。實驗結果除了顯示此平台之測試機制可在以ARM處理器為基礎之系統發展板上正確執行之外，同時亦顯示此測試平台具有隨插即用之特性，矽智產電路可以相當簡單之之方式整合至此測試平台並進行驗證。這些結果充分證實了本論文各項成果之有效性及實用性。

With the advance of IC fabrication technology, the SOC (System-on-a-chip) design methodology is becoming the main stream of IC design. In this novel concept, a wide range of designs, including logic, processor, memory and analog devices, are integrated into a single chip so as to greatly reduce product cost and shorten time-to-market. This design methodology, however, also induces many challenges, one of which is SOC testing.
In order to address this problem, an SOC test platform has been developed in our previous work. This test platform employs the embedded processor to control the SOC test flow and a novel test access mechanism (TAM) controller to carry out the test procedures. Software-oriented and hardware-oriented test procedures have both been developed to achieve a highly flexible and efficient testing of SOC designs. Based on this work, in this thesis we focus on 1) implementing this test platform with ARM-based integrator board so as to verify the correctness of the test mechanism in this platform at a more realistic level and 2) separating the test mechanism and cores under test on different FPGAs provided by the ARM-based integrator to convert the prototyping of this test platform into an SOC development environment. In this system, the user can verify not only the functions of an IP under normal mode, but also those under test mode, which is one of the most remarkable novelties of this work. From the experimental results, we show that the test mechanism is correctly emulated in the ARM-based integrator platform. Moreover we also show that IPs can be easily integrated into this system using a plug-and-play manner and then be verified. These results validate both the effectiveness and the practicability of this work.

[1] Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong, “An Embedded Processor Based SOC Test Platform,” in Proc. ISCAS, pp.2983-2986 ,2005.
[2] Yu-Ting Hung and Kuen-Jong Lee, “An Embedded-Processor-Driven Platform for SOC Testing,” in Proc. VLSI Design/CAD Symposium, 2002.
[3] Ming–Long Wu and Kuen-Jong Lee, “Performance Analysis and Enhancement of SOC Test Platforms”, NCKU master thesis, 2005.
[4] ARM Technology Web Site, http://www.arm.com/.
[5] AMBA Specification Technology, http://www.arm.com/.
[6] IEEE Computer Society, “IEEE Std. 1149.1: IEEE Standard Test Access Port and Boundary-Scan Architecture”, 1990.
[7] IEEE Computer Society, “1500 IEEE Std. Testability Method for Embedded Core-based Integrated Circuits”, 2005.
[8] Sheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang and Kuen-Jong Lee, “A High Speed BIST Architecture for DDR-SDRAM Testing” in Proc. Int’l workshop on Memory Tech., Design and Test, pp. 52-57, 2005.
[9] Kuen.-Jong Lee and Cheng-I Huang, “A Hierarchical Test Control Architecture for Core Based Design,” in Proc. Asian Test Symp., pp. 248-253, 2000.
[10] Vikram Iyengar and Krishnendu Chakrabarty, “Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip”, in Proc. VLSI Test Symp., pp. 368-374, 2001.
[11] Yu-Ting Hung and Kuen-Jong Lee “An Embedded-Processor-Driven Platform for SOC Testing”, NCKU master thesis, 2002.
[12] Li Chen, “Software-Based Self-Testing Methodology for Processor Cores”, in Proc. Int’l Test Conf., pp.369-380, 2001.
[13] Ching-Hong Tsai and Cheng-Wen Wu, “Processor-Programmable Memory BIST for Bus-connected Embedded Memories,” in Proc. Asia and South Pacific Design Automation Conf., 2001.
[14] Ozgur Sinanoglu and Alex Orailoglu, “Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test,” in Proc. Asian Test Symp., pp. 202-207, 2003.
[15] SynTest, Turbo BIST-Memory User Guide, http://www.syntest.com/.
[16] Synopsys Technology Web Site, http://www.synopsys.com/.
.
[17] QuartusII Technology Web Site, http://www.altera.com/
[18] SSRAM of integrator/AP data sheet Web Site, http://www.arm.com/pdfs/
[19] Jacob and Savir, “Shrinking Wide Compressors,” IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, vol. 14, no. 11. pp. 1379-1387, 1995.
[20] Loganathan Lingappan and Niraj Ke Jha, “Unsatisfiability based Efficient Design for Testability Solution for Register-transfer Level Circuits,” in Proc VTS, pp. 418-423, 2005.
[21] Yu-Tai Chang and Chin-Liang Wang, “New systolic array implementation of the 2-D discrete cosine transform and its inverse,’’ IEEE Trans. Circuits Syst. Video Technol., vol 5, Issue 2, pp. 150-157, Apr. 1995.
[22] Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, Akihiro Shimizu, “A 3.8-ns CMOS 16×16-b Multiplier Using Complementary Pass-Transistor Logic,” IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 388-395, 1990.