<P>近年來，橫向雙擴散金氧半場效電晶體已被廣泛地應用在高壓整合積體電路當中。這是由於它的製程和傳統的低壓元件相容。在某些應用中，元件操作在高閘極及高汲極電壓下，因此熱載子可靠度是重要的議題。本篇論文，將會針對橫向雙擴散金氧半場效電晶體之熱載子可靠度做詳細的探討。
<P>首先，就12V操作電壓的厚氧化層LDMOS元件，其基板電流隨著閘極電壓增加而一直上升，這意味著柯爾克效應在閘極電壓很低時，就已經相當的嚴重。另外，在不同的閘極偏壓stress下，藉由模擬及實驗的結果，發現有兩種不同的退化機制存在這個元件當中。而元件的參數像是最大轉導、導通電阻在經過低閘極電壓及高閘極電壓stress過後，其退化的結果也支持我們所提出的理論。同時，此元件的飽合電流在經過低閘極電壓stress過後，發現電流值有異常上升的現象。
<P>為了增加元件的壽命，也使用到n型漂移區較長的元件，由於橫向電場大量下降，使得元件的各參數退化降低許多。元件的基板電流在閘極電壓較低時，有效地降低許多。換句話說，漂移區較長的元件能使柯爾克效應延遲發生。另外，實驗的結果發現此元件的損傷被較均勻地分布在漂移區及通道區當中。
<P>最後，視應用的不同，有許多不同氧化層厚度的LDMOS元件被設計。此部份，將針對薄氧化層的LDMOS電晶體元件之熱載子可靠度做探討。實驗的結果發現，在不同閘極電壓stress下，兩種不同的退化機制在主導元件導通電阻的退化。一個機制會使退化上升，但另一個機制會使得退化下降。

<P>In recent years, LDMOS transistors have been widely used in high voltage integrated circuits (HVIC). That’s due to its process flow being compatible with low voltage CMOS devices. In some applications, LMDOS transistors operate under high gate and drain voltage, thus hot carrier reliability becomes a serious concern. In this thesis, hot carrier reliability of LDMOS transistors will be investigated in detail.
<P>First of all, LDMOS transistors designed to operate at Vds=12V are studied. Substrate current (Isub) of the devices continually increases as measure gate voltage, thus indicates that Kirk effect is significant even at low gate voltage region. In addition, based on experiment and simulation results, two degradation mechanisms are observed in this device at low and high gate stress voltage. The degradation of device parameters such as Gm(max), on resistance(Ron) also supports our theory. At the same time, anomalous increase of saturation current (Id(sat)) is observed after low gate voltage stress.
<P>To improve the lifetime of the LDMOS transistors, devices with longer drift region length (Ld) are also investigated. Owing to the large decrease of lateral electric field, degradation of device characteristics is significantly reduced. Isub in longer Ld device is also much lowered at low gate voltage region. In other words, it implies that Kirk effect occurs later in longer Ld devices. Moreover, based on experiment results damage is more uniformly distributed in the channel and drift region in this device.
<P>Finally, depending on the various applications, devices with different gate oxide thickness are designed. In this part, hot carrier reliability of LDMOS transistors with thin gate oxide will be investigated. Based on experiment results, two competing mechanisms dominate the Ron degradation at low and high stress gate voltage. One mechanism will lead to the increase of Ron degradation, while the other one will result in the decrease of Ron degradation.

[1]B.J. Baliga, “An overview of smart power technology,” IEEE Elect. Dev., Vol.38, pp.1568, July 1991.
[2]C. Contiero, P. Galbiati, and M. Palmieri, “Characteristics and applications of a 0.6μm Bipolar-CMOS-DMOS technology combing VLSI nonvolatile memories,”IEDM Tech. Dig., pp.465, 1996.
[3]A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, and C. Contiero, “LDMOS implementation in a 0.35μm BCD technology (BCD6),”ISPSD, pp.323, 2000.
[4]E.C. Griffith et. al., “Characterization and modeling of LDMOS transistors on a 0.6μm CMOS technology,” ICMTS, pp.175-180, 2000.
[5]P. Hower, J. Lin, S. Haynie et. al., “Safe operating area considerations in Ldmos transistors,” ISPSD, pp.55-58, 1999.
[6]P.L. Hower, J. Lin, and Steve Merchant, “Snapback and safe operating area of Ldmos transistors,” IEDM Tech. Dig., pp.193-196, 1999.
[7]S. K. Lee, C. J. Kim, J. H. Kim, Y. C. Choi, H. S. Kang, and C. S. Song, “Optimization of safe-operating-area using two peaks of body-current in submicron LDMOS transistors,” ISPSD, pp. 287, 1998.
[8]R. Versari, A. Pieracci, “Experimental study of hot-carrier effects in LDMOS transistors,” IEEE Trans. Electron Devices, vol. 46, no. 6, pp. 1228, June 1999.
[9]M. S. Shekar, R. K. Williams, M. Cornell, M.-Y. Luo, and M. Darwish, “Hot electron degradation and unclamped inductive switching in submicron 60-V lateral DMOS,” IRPS, pp. 383, 1998.
[10]A. W. Ludikhuize, M. Slotboom, A. Nezar, N. Nowlin, and R. Brock, “Analysis of hot-carrier-induced degradation and snapback in submicron 50V lateral MOS transistors,” ISPSD, pp. 53, 1997.
[11]R. Versari, A. Pieracci, S. Manzini, C. Contiero, and B. Ricco, “Hot-carrier reliability in submicron LDMOS transistors,” IEDM Tech. Dig., pp. 371, 1997.
[12]S. Manzini, A. Gallerano, and C. Contiero, “Hot-electron injection and trapping in the gate oxide of submicron DMOS transistors,” ISPSD, pp. 415, 1998.
[13]S. Aresu, W. De Ceuninck, G. Van den bosch et. al., “Evidence for source side injection hot carrier effects on lateral DMOS transistors,” Microelectronics & Reliability, vol.44, pp.1621, 2004.
[14]L. Labate, S. Manzini, and R. Roggero, “Hot-Hole-Induced dielectric breakdown in LDMOS transistors,” IEEE Trans. Electron Devices, vol. 50, no. 2, pp.372, February, 2003.
[15]C. Hu, S. C. Tam, F.-C. Hsu, P. K. Ko, T.-Y. Chan and K. W. Terrill, “Hot-electron-induced MOSFET degradation - model, monitor, and improvement,” IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 375, 1985.
[16]C. Hu et. al. “Hot-Carrier effects,” Chap3, in Advanced MOS Device Pyhsics, vol. 18, pp. 119-160, 1989
[17]A. W. Ludikhuize, “Kirk effect limitations in HV IC’s,” ISPSD, pp. 249, 1994.
[18]D. Brisbin, A. Strachan, and P. Chaparala, “Optimizing the hot carrier reliability of N-LDMOS transistor arrays,” Microelectronics & Reliability, vol. 45, pp. 1021-1032, 2005.
[19]P. Moens, M. Tack, R. Degraeve, and G. Groeseneken, “A novel hot-hole injection degradation model for lateral nDMOS transistors,” IEDM Tech. Dig., p. 877, 2001.
[20]P. Moens, G. Van den bosch, and G. Groeseneken, “ Competing hot carrier degradation mechanisms in lateral N-type DMOS transistors,” IRPS, p.214, 2003.
[21]A. Shibib, et. al., “ Control of hot carrier degradation in LDMOS devices by a dummy gate field plate: experimental demonstrations,” ISPSD, pp. 233, 2004.
[22]F. Bauwens, and P. Mones, “Locating hot carrier injection in n-type DeMOS transistors by charge pumping and 2D device simulations,” Microelectronics & Reliability, vol. 44, pp. 1625-1629, 2004.
[23]D. Brisbin, A. Strachan, and P. Chaparala, “Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications,” IRPS, pp. 105, 2002.
[24]P. Mones, G. Van den bosch, et. al., “Hot hole degradation effects in lateral nDMOS transistors,” IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1704, 2004.
[25]S. Chen, J. Gong et al., “Time-dependent drain- and source-series resistance of high-voltage lateral diffused metal-oxide-semiconductor field-effect transistors during hot-carrier stress,” Jpn. J. Appl. Phys., vol. 42, pp. 409-413, 2003.
[26]M. Knaipp, G. Rohrer, R. Minixhofer, and E. Seebacher, “Investigations on the high current behavior of lateral diffused high-voltage transistors, ” IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1711, 2004.
[27]J. F. Chen and C.-P. Tsao, “Convergence of hot-carrier-induced saturation-region drain current and linear-region drain current degradation in advanced n-channel metal-oxide-semiconductor field-effect transistors,” Applied Physics Letters, vol. 83, no. 9, pp. 1872-1874, 2003.
[28]M. Annese, S. Carniello, and S. Manzini, “Design and optimization of a hot-carrier resistant high-voltage nMOS transistor,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1634, 2005.
[29]J. F. Chen, K.-M. Wu, K.-W. Lin, Y.-K. Su, and S. L. Hsu, “Hot-carrier reliability in submicrometer 40V LDMOS transistors with thick gate oxide,” IRPS, pp. 560-564, 2005.