積極地降低功率消耗是發展無線系統的重要趨勢。尤其對於微小化的無線感知網路以及生醫感測元件而言，低電壓的積體電路是這些低功率系統不可缺少的核心元件。然而，低電壓的電路設計面臨許多來自元件、電路與系統設計的挑戰，尤其是當電壓降低到接近電晶體的臨界電壓時，操作電流和相關的電路特性對於製程, 操作電壓和溫度等參數變異將呈現指數的相依性，所以在必須在晶片內設計動態適應的機制。但是由於整體系統仍必須符合十分緊縮的功率消耗標準，使得同時考量變異控制與降低功率的設計變得更具有挑戰性。本文因此深入探討關於低電壓、低功率電路與系統的設計和研發，除了對於相關技術作完整的檢視與分析之外，更提出數種從理論到電路上的改進。其研發重點摘要如下。首先，本文提出一個有效而且適應性的最低可操作電壓計算，使得最低可操作電壓可以根據實際製程和環境變異而調整。其次，本文提出一個多功能的變異控制設計，並且大幅度降低這種控制所需要消耗的功率。本文也提出了能工作於超低電壓、具備製程變異容忍的記憶體，此記憶體中的新式電路能有效降低因為隨機製程變異所造成的讀取錯誤率。最後，本文探討低電壓電路與一般電壓電路的介面設計、審視相關電路與系統的設計議題、並提出數種改進的新式電路。以上所提出的理論和新式電路設計皆經過嚴謹的模擬或實體晶片開發驗證，證明可以有效提升低電壓系統的堅實和穩定性。

Low power consumption is essential for the devices in wireless sensor networks and biomedical body-area networks, because such devices usually have miniature dimensions and demanding requirements in lifetime. Aggressively and dynamically scaling down the operating voltage of the digital components is a practical method to optimize the power consumption according to the dynamic performance requirement. However, the major challenge of the low-voltage circuits is their high sensitivity to process, voltage, and temperature variations, which are caused by the manufacturing processes and operating environments. The variations greatly affect the performance and signal integrity of the low-voltage circuits, and their impact is exponential when the supply voltage is scaled down to the subthreshold. Robust and adaptive designs thus are crucial challenges. Furthermore, the overall power budget remains although the adaptive designs are included. This dissertation discusses the research and developments of the low-voltage and variation-aware circuits and storage elements. The important achievements are organized as follows. First, this dissertation proposes a low-complexity calculation of the minimum supply voltage considering the limited power budget and dynamic variations. Second, ultra-low-power adaptive-body-bias circuits are proposed to compensate for the process variations, where the proposed circuits support various power-management strategies, and the power consumption is at the leakage level. In addition to the low-voltage logics, a robust subthreshold memory is proposed considering the serious access failure due to within-die variations. Finally, this dissertation proposes level-converting flip-flops considering the clocking and loading effects of performance-constrained multiple-supply systems. Robust level conversion from sub-to-super-threshold voltage is also analyzed and studied. Abovementioned research and developments are verified with corresponding simulations and measurements.

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