成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	林辰諺 Lin, Chen-Yen
論文名稱：	即時可重置之多位元寬度算術單元設計與實現 Design and Implementation of a Run-Time Reconfigurable Multi-Width Functional Unit
指導教授：	周哲民 Jou, Jer-Min
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	76
中文關鍵詞：	功能單元、可重置、即時
外文關鍵詞：	Reconfigurable, Run-Time, Functional Unit
相關次數：	點閱：71 下載：2
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

由於整合了各種不同領域的應用在一個系統上，系統必需執行多種位元寬度的算術運算和滿足高性能計算的需求。因此，在本論文中提出一個具有比傳統算術單元更有彈性與高性能的可重置功能單元(rMWFU)。此設計可以動態的使用硬體資源去處理8位元, 16 位元與32 位元算術運算以及處理DSP應用資料流的能力。此外，我們提出一個包含可重置功能單元的可即時重置硬體，可作為一個協同處理單元或處理器的運算單元使用，來提昇多媒體應用系統的運算能力。實驗的結果顯示出我們所提出的設計可以提升DSP應用的效能。

Owing to the integrated applications of various domains in a system, the system is required to perform different bit-width arithmetic operations and meet high performance computing demand. Therefore, we propose a novel reconfigurable multi-width functional unit (rMWFU) that has higher performance and flexible than the traditional function units. This design can dynamic use the hardware resources to process 8-bit, 16-bit and 32-bit arithmetic operations. In addition, the full or partial data flow of DSP applications can be performed in proposed design. We also propose a run-time reconfigurable hardware with rMWFU which can be used as a co-processing unit or a function unit in general-purpose processors to accelerate multimedia application. The experimental result shows this design will improve the performance of DSP applications.

Chapter 1. Introduction.................................................1
Chapter 2. The Reconfigurable Computing Systems.........................4
　2.1 Coupling of Reconfigurable Computing System.......................6
　2.2 Granularity of Reconfigurable System..............................9
　2.3 Reconfigurability of Reconfigurable System........................10
　2.4 Depth of Programmability of Reconfigurable System.................11
　2.5 Self Reconfigurable computing systems.............................11
Chapter 3. Reconfigurable Booth Multiplier Concept......................12
　3.1 Booth Multiplication and Multiply-Add Operation...................13
　　3.1.1 Booth Encoder and Decoder.....................................14
　　3.1.2 Compressor of Booth Multiplication............................15
　　3.1.3 Multiply-Add Operation........................................16
　3.2 Reconfigurable Booth Multiplication...............................17
　3.3 Reconfigurable Carry Save Adder of Booth Multiplier...............20
Chapter 4. Reconfigurable Multi-Width Functional Unit...................22
　4.1 Architecture of Reconfigurable Multi-Width Functional Unit........23
　4.2 The Fields of Context Word........................................24
　4.3 Reconfigurable Booth Unit Block...................................26
　　4.3.1 Reconfigurable Carry Save Adder Structure.....................27
　　4.3.2 Reconfigurable 16-bit/8-bit Fast Adder........................32
　　4.3.3 Function Decoder..............................................33
　　4.3.4 Reconfigurable Booth’s Partial Products Generator............34
　　4.3.5 Block Data Input Manger and Data Output Manger..........35
　4.4 Interconnection Networks..........................................37
　4.5 Parallel Data Input and Output Interface..........................41
Chapter 5. Run-Time Reconfigurable Hardware with rMWFU............43
　5.1 Run-Time Reconfigurable Hardware Architecture.....................44
　5.2 Context Buffer Group..............................................45
　5.3 Input Buffer......................................................46
　5.4 Output Buffer Group...............................................47
　5.5 rMWFU Control Unit................................................48
Chapter 6. Application Examples and Performance Evaluation........50
　6.1 Application Examples..............................................50
　　6.1.1 FIR Filter Mapping............................................51
　　6.1.2 4-Points Discrete Cosine Transform Mapping....................55
　　6.1.3 Matrix-Vector Multiplication Mapping..........................60
　6.2 SignalWAVe Platform...............................................65
　6.3 Performance Evaluation............................................66
Chapter 7. Conclusion and Future Work...................................73
Reference...............................................................75
                                    

[1]Simon D. Haynes, Antonio B. Ferrari, P.Y.K. Cheung, “Flexible Reconfigurable Multiplier Blocks for Enhancing the Architecture of FPGAs”, Custom Integrated Circuit Conference, CICC'99.

[2] Keith Reeves, Ken Sienski, Calvin Field, “Reconfigurable Hardware Accelerator for Embedded DSP,” Reconfigurable Computing Conference, 1996

[3] Guangming Lu. “Modeling, Implementation and Scalability of the MorphoSys Dynamically Reconfigurable Computing Architecture”, Doctor of Philosophy in Electrical and Computer Engineering University of California, Irvine, 2000.

[4] T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung “Reconfigurable computing: architectures and design methods”, IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 2, March 2005

[5] Katherine Compton, Scott Hauck, “Reconfigurable Computing: A Survey of Systems and Software”, ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171–210.

[6] Ming-Tsai Chan, Robert C. Chang, “High-Speed Booth Multiplier Design”, M.Sc. Thesis in Electrical Engineering of National Chung Hsing University, 2002

[7] Jer-Min Jou. "Reconfigurable SoC Architectures," Proceedings of the 2003 VLSI Design/CAD Symposium, 2003.

[8] R. Tessier and W. Burleson, “Reconfigurable Computing for Digital Signal Processing: A Survey”, in Journal of VLSI Signal Processing, May/June 2001, pp 7-27.

[9] Behrooz Parhami. “Computer Arithmetic Algorithms and Hardware Designs”. Oxford, 2000.

[10] Mi Lu, “Arithmetic and Logic in Computer Systems”, Wiley Interscience, 2004.

[11] J.-F. Li and Y.-J. Huang, "A Design Methodology for Carry Look-Ahead Adders with Reconfigurability," in Proc. 16th VLSI/CAD Symp., (Hualien), Aug. 2005

[12] Hao-I Yang, Jer-Min Jou, “Run-Time Reconfigurable Superscalar Processor Design”, M.Sc. Thesis in Electrical Engineering of National Cheng Kung University, 2005

[13] Hong-Yi Su, Jer-Min Jou, “Run-Time Reconfigurable Hardware Platform Design for Multimedia Applications.” M.Sc. Thesis in Electrical Engineering of National Cheng Kung University, 2005

[14] Zabel, M. Kohler, S. Zimmerling, M. Preusser, T.B. Spallek, R.G., “Design Space Exploration of Coarse-Grain Reconfigurable DSPs”, International Conference on Reconfigurable Computing and FPGAs, pp. 15-22, Sept. 2005

[15] Xilinx: Xilinx ISE 6 Software Manuals, www.xilinx.com

[16] Code Composer Studio User’s Guide, www.ti.com

[17] ARM Developer Suite Debug Target Guide, www.arm.com

[18] http://www.lyrtech.com/DSP-development/dsp_fpga/signalwave.php

校內：2007-08-25公開
校外：2010-08-25公開

簡易檢索 / 詳目顯示

相關論文