成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	林郁軒 Lin, Yu-Xuan
論文名稱：	基於網路介面之可重構網路單晶片路由器設計 Design of a Reconfigurable NoC Router with AMBA-based Network Interface
指導教授：	周哲民 Jou, Jer-Min
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	73
中文關鍵詞：	網路介面、路由器
外文關鍵詞：	NoC, router, circuit switching, wormhole switching, network interface, TDM, virtual channel
相關次數：	點閱：233 下載：1
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

網路單晶片(NoC)是一個可以解決複雜單晶片系統(SoC) 設計的系統平台(template)。在本論文中將介紹晶片上的網路架構並提出一個可以保證傳輸頻寬與最高使用效率的網路單晶片路由器。以結合兩種資料傳輸: 線路式交換技術(Circuit Switching)與蟲洞式交換技術(Wormhole Switching)方式來實現之。
在線路式交換技術中搭配使用分時多工(TDM)來降低佔線問題並增進在網路上通道的重複使用。此外加上了擁有虛擬通道的蟲洞式交換技術來使得網路的使用率達到最高。為了使整合網路單晶片系統更加容易，我們附加了一個具AMBA AHB協定的網路介面。
本論文所提出的路由器包含五個32bits輸入輸出端可運作至100MHz，頻寬可達到16Gbps。這樣的性能已經足夠於映射在NoC上的HDTV的應用。

Networks-on-a-chip (NoC) is a new system template, which helps to meet many of challenges of designing a complex system-on-a-chip (SoC). In the thesis, we introduce the on-chip network and propose the router for NoC which provides both guaranteed and best-effort communication services.
We adopt the Time-Division-Multiplexing (TDM) technique for circuit switching to reduce the channel occupied problem and to improve the reuse of channels in the network, and use reconfigurable recording table to complete TDM technique. In order to sufficiently utilize the bandwidth of the network we add the wormhole switching which contains several virtual channels. Additionally, we append the standard interface with AMBA AHB into our NoC router for easier integration of the processing elements (PEs) of NoC.
The benchmark router with 5 32-bit ports can operate at 100MHz and the bandwidth of router can be up to 16Gbps. The performance of the router is enough for providing an HDTV application on NoC.

CHAPTER 1 INTRODUCTION.....................................................1
CHAPTER 2 INTERCONNECT NETWORK FRAMEWORK...................................5
1 LAYERED PROTOCOL STACK MAPPING ON NOC................................5
2 CLASSIFICATION OF NETWORKS...........................................7
2.1 Share-Medium network.............................................8
2.2 Indirect network.................................................8
2.3 Direct network...................................................9
3 SWITCH TECHNOLOGY OF NETWORKS.......................................10
3.1 Circuit switching...............................................10
3.2 Packet switching................................................11
4 ROUTING ALGORITHM...................................................17
5 THE PROPOSED METHOD IN OUR NOC......................................18
CHAPTER 3 DESIGN OF A NOC ROUTER..........................................19
1 ROUTER OVERVIEW.....................................................19
1.1 Building a circuit switching link...............................20
1.2 Reconfigurable circuit switching link...........................21
2 WORMHOLE SWITCHING ARCHITECTURE IN OUR NOC ROUTER...................22
2.1 Flow of a Packet Traversing the WH architecture of our Router...24
2.2 Wormhole Switching Architecture.................................25
2.3 Setup Packet transmission.......................................36
3 CIRCUIT SWITCHING ARCHITECTURE IN OUR NOC ROUTER....................37
3.1 Input_buffer Table..............................................39
3.2 Input_direction Table...........................................40
3.3 Additional mechanism for masking wormhole switching.............41
4 ARCHITECTURE OF OUR NOC ROUTER......................................43
5 PACKET FORMAT.......................................................44
CHAPTER 4 AMBA-BASED NETWORK INTERFACE DESIGN.............................46
1 ADDRESS OF THE NETWORK-ON-CHIP......................................46
2 FUNCTIONS OF NETWORK INTERFACE......................................48
3 AMBA-AHB SPECIFICATION..............................................51
3.1 AMBA System.....................................................51
3.2 Signal Definition...............................................51
3.3 Arbitration signals.............................................53
3.4 Transfer Types and Slave Responses Types........................53
4 ROUTER PROTOCOL SPECIFICATION.......................................54
5 DESIGN OF THE PROPOSED NETWORK INTERFACE............................55
5.1 Fetch architecture..............................................56
5.2 Convey architecture.............................................56
5.3 Internal handshaking............................................58
CHAPTER5 RESULTS..........................................................62
1 SIMULATION OF WORMHOLE SWITCHING....................................62
2 SIMULATION OF CIRCUIT SWITCHING.....................................63
3 SIMULATION OF NETWORK INTERFACE.....................................65
4 SYNTHESIS REPORT....................................................67
CHAPTER6 CONCLUSION.......................................................70
REFERENCE.................................................................72
                                    

[1] L. Benini and D. Bertozzi, “Networks-on-Chip architectures and design methods,” IEE Proc. – comput. Digit. Tech., Vol. 152, No. 2, March 2005, pp. 261-272
[2] Jer-Min Jou et al. “Adaptive Network-on-a-Chip Architecture System Design”, the 46th IEEE International Midwest Symposium on Circuits and Systems, 2003.
[3] L. Benini and G. De Micheli, “Networks on Chip: A New Paradigm for Systems on Chip Design,” Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, Paris, France, March 2002, pp. 418-419.
[4] Guerrier, P., and Greiner, A.: ‘A generic architecture for on-chip packet-switched interconnections’. Proc. Design Automation and Test in Europe Conf., Paris, 2000, pp.250–256.
[5] L. M. Ni, “Issues in designing truly scalable interconnection networks,” proceedings of the 1996 ICCP Workshop on Challenges for Parallel Processing, pp.74-83, August 1996.
[6] Li-Shiuan Peh and William J. Dally, “A delay model and speculative architecture for pipelined routers”, International Symposium on High-Performance Computer Architecture, Jan., 2001.
[7] Shih-Hsun Hsu, et al. “An Efficient NoC Pipelined Router Design”, ICCCE '06, 2006.
[8] Shin-Hsun Hsu, “Design and Implementation of a Router for Network-on-Chip” NCKU, R.O.C thesis for Master of Science, June 2005.
[9] “AMBATM Specification Revision 2.0”, May 13, 1999.
[10] Yuan-Chin Wu, “Systematic Design and Implementation of SoC Interface IPs”, NCKU, R.O.C thesis for Master of Science, July 2004.
[11] J. Liu, L. R. Zheng and H. Tenhunen, “A Guaranteed-Throughput Switch for Network-on-Chip,” Proceedings of International Symposium on System-on-Chip, Nov. 2003.
[12] P. T. Wolkotte, Gerard J. M. Smit, Gerard K. Rauwerda, L. T. Smit,”An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip”, 19th IEEE International Parallel and Distributed Processing Symposium, 2005.
[13] J. Kim, D. Park, T. Theocharides and N. Vijaykrishmam, “A Low Latency Router Supporting Adaptivity for On-Chip Interconnects”, DAC 2005, June 13-17.
[14] Chia-Ming Wu, Sung-Tze Wu, and Hsin-Chou Chi “Design of A Versatile Hybrid Switch for On-Chip Networks”, the 16th VLSI Design/CAD Symposium, 2005.
[15] Brian Gold, “Balancing Performance, Area, and Power in an on-chip-Network”, master thesis of the Science in Computer Engineering Department, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, July, 2003.
[16] William J. Dally, “Virtual-Channel Flow Control”, IEEE Transactions on Parallel and Distributed System, vol. 3, No. 2, March, 1992.
[17] ARM Design Kit, http://www.cic.org.tw

2007-08-24公開

簡易檢索 / 詳目顯示

相關論文