現今運動控制IC的開發可分為兩大方向，分別為整合型運動控制IC與專用型運動控制IC，不論那一類型，在開發過程中皆可劃分為不同任務類型的區塊，這些區塊可將其設計成智慧技術元件(Intellectual Properties；IP)。本論文之主要目的即為發展運動控制系統中關於運動命令規劃的各式IP，並提供相關開發經驗給運動控制IC設計者，使其能快速的整合各類IP以縮短開發時程，完成所需不同功能之運動控制IC。
　　在運動命令規劃方面，加減速規劃、脈波命令輸出與NURBS曲線的產生皆為重要課題，於本論文中，將分別探討這三種任務類型區塊於運動命令規劃IP的設計與實現。首先，對於加減速規劃方面，採用數位迴旋積分方式實現具有梯型與S Curve兩種加減速規劃的IP，相較於傳統多項式加減速規劃，本論文中所採用的方法具有容易規劃、零誤差的優點。對於脈波命令輸出方面，採用數位差分法(Digital Difference Analyzer；DDA)實現具有均勻脈波命令輸出的IP，相較於傳統DDA脈波命令架構，本論文中修改之DDA脈波命令架構具有可變週期的優點。此外NURBS (Non-Uniform Rational B-Spline)參數式曲線，本論文採用去零化簡運算之技巧予以實現，可大幅化簡運算的次數。相較於傳統樹狀結構運算法，本論文中所採用的方法具有高效能、省空間的優點。
　　基於開發測試的便利性與成本的考量下，本論文以現場可規劃閘陣列(Field Programmable Gate Array；FPGA)作為發展之平台，並以硬體描述語言(VHSIC Hardware Description Language；VHDL)的方式實現所設計之運動命令規劃IP。

　　The motion control ICs can be divided into two categories-integrated and specific. Both types of ICs consist of several sub blocks. These sub blocks can be designed into Intellectual Properties (IP). The aim of this thesis is to develop different kinds of IP for motion planning. It is expected that, through this thesis, the development experience can be shared with the motion control designers so that the time duration for developing different motion control ICs can be shortened by integrating different kinds of IP more quickly.
　　It is known that acceleration/deceleration motion planning, pulse command generation, and generation of NURBS curves are all important subjects in motion planning. The design and implementation of IP for these subjects will be addressed in this thesis. First of all, the digital convolution technique is exploited to develop IP for trapezoid and S curve Acceleration/ Deceleration motion planning. Compared with the conventional polynomial type methods, the proposed approach has advantages such as easy formulation and error free. For pulse command generation, the Digital Difference Analyzers (DDA) is used to implement the IP that can output the pulse commands smoothly. Compared with the conventional methods, the advantage of the proposed approach is that the sampling period of DDA is adjustable. In addition, a more efficient way to implement the NURBS (Non-Uniform Rational B-spline) parametric curve is employed to reduce the number of computation. Therefore, the proposed approach has advantages such as high efficiency and space saving compared with the commonly used tree structure-based approach.
　　In this thesis, considering the issues such as convenience and cost for developing IP, the Field Programmable Gate Array (FPGA) is adopted as a platform for development. In addition, the developed IP for motion planning is implemented using the VHSIC Hardware Description Language (VHDL).

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