在這篇論文當中，我們實現了一用於H.264/AVC baseline profile 裡高效能低成本的熵編碼器。在我們提出的設計中，利用一有效率統計適應性可變動長度編碼器的編碼資訊方法及簡單規律性的nC 計算架構，利用這些方法能有效減少電路所需面積且能具有不錯的編碼效能。我們使用TSMC 0.18μm 製程技術合成出來的電路只需16K
gates，電路工作頻率為100Mhz，而在27MHz 及1.8V 環境下電路消耗功率為2.41mW，因此我們所提出的設計非常適合於多媒體行動裝置及高畫質數位電視即時處理。
另一個設計的重點為驗證電路，在編碼流程中有太多可能的組合會發生，若我們僅用幾個影像序列來驗証，我們無法很有信心的確定我們的電路是正確的，因此我們利用三種層級驗證方法來提高我們對電路的信心。這些方法包括：電路功能驗證、系統層級驗證及FPGA 驗證，最後結果顯示我們的電路能在系統中正常運作。

This thesis presents a high performance and low cost architecture for H.264/AVC baseline profile Entropy Encoder. In the proposed design, an efficient method for encoding the block symbols in CAVLC and simple nC calculation through the consideration of statistical and regularity properties is proposed in the designed architecture. By these methods, the circuit area can effectively reduce and have good coding performance. With
the synthesis constraint of 100Mhz clock, the logic gate count of the proposed design is 16K gates based on a 0.18μm TSMC cell library. The power consumption of the proposed
hardware is 2.41mW at 27Mhz and 1.8V. The implemented architecture can achieve the real-time processing requirement for multimedia handheld mobile devices and HDTV.
The other major point of design is verification. In the encoding flow, there are too many different combinations. While only several sequences were used for testing it, the
confidence of the proposed Entropy Encoder was not enough. So difference level verification method was designed to test the Entropy Encoder to get higher confidence. This method included Function Verification, System Level Verification and FPGA Verification. Finally, the result reveals that it can work correctly on a system.

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