本篇論文主要是提出一高解析度多音頻訊號產生器的設計方法。首先，針對對電路元件變動有著低敏感度的四階跳蛙超取樣類比/數位轉換器，提出一快速又有效率的設計方法。藉由一連串的理論分析，可以把控制系統穏定的係數限制到一個稱為穏定區的範圍內。由於現今電路都操作在低電壓，因此對轉換器中積分器的輸出範圍加以 2伏特的限制後，我們可以把穏定區的範圍縮小到一個所謂的絕對穏定區的範圍內。再利用程式的模擬找出會產生最佳訊號對雜訊比的一組係數。模擬的結果顯示，以超取樣率256倍可得訊號對雜訊比是105 dB和動態範圍是100 dB。根據模擬的結果，此系統不僅是穏定且有效率的，同時也適合應用於一些需要高解析度的電子電路上。
其次，利用前面所發展出的類比/數位轉換器可以更進一步地設計出一高解度多音頻訊號產生器。所發展出來的訊號產生器是由一傳統的共振器開始。為了避免係數過小，此傳統的共振器經過修改後，加上前面所發展的類比/數位轉換器就建構出一高解度單音頻訊號產生器。再利用通信上常用的時間分割多工技術來建構出高解度多音頻訊號產生器。最後，以一雙音頻訊號產生器為例，在20 KHz的基頻下訊號對雜訊比高達90 dB。因此本論文所發展出來的高解度多音頻訊號產生器非常適合應用於高解析度的訊號處理系統中，例如自我測試系統、通信系統和任意訊號產生器。

In this thesis, a novel methodology for designing and analyzing high performance sigma-delta leapfrog modulators for ultra-high resolution analog-to-digital (A/D) converters is presented. The less sensitive topology, the leapfrog topology, in component variations is analyzed by considering the noise transfer function (NTF). By using theoretical analysis, the loop coefficients are constrained to a small, clear and definite range called the stable region. With the output voltage limited within 2V, an absolute stable region (ASR) is obtained. A program that analyzes and generates the required coefficients is constructed for easily designing of this topology. For a 256 over-sampling ratio (OSR) and the coefficients from ASR, the signal to noise ratio (SNR) and dynamic range (DR) are 105 dB and 100 dB, respectively. In accordance with the behavior simulation results, the system is not only stable and efficient but also suitable for high-resolution applications.
Furthermore, a novel technique for analyzing and designing a high performance multi-tone signal generator is presented. The proposed multi-tone signal generator begins with two parallel integration units and four coefficients. In order to avoid containing coefficients that are too small, two of the coefficients remain constant while the others are variable. The theoretical analysis illustrates that the coefficients and the initial values of integration units determine the oscillation frequency and amplitude, respectively. A 4th-order leapfrog sigma-delta modulator that follows the resonator to shape the noise floor is proposed for constructing the signal generator. An useful technique called the time-division multiplexing (TDM) is adopted for generating multi-tone oscillation because of the great hardware overhead. An example is used to demonstrate that a two-tone oscillator with the TDM technique is able to achieve a SNR over 90 dB within the 20 kHz base-band. The proposed multi-tone oscillator can be used in high-resolution signal processing systems such as self-test applications, telecommunications, and arbitrary signal generation.

[1] H. Inose, Y. Yasuda, and J. Murakami, “A telemetering system by code modulation – sigma-delta modulation,” IRE Trams. Space Electron. Telem., vol. SET–8, pp. 204–209, Sept. 1962.
[2] J. C. Candy, “A use of limit cycle oscillations to obtain robust analog-to-digital converters,” IEEE Trans. Commun., vol. COM–22, pp. 298–305, Mar. 1974.
[3] R. C. Brainard, and J. C. Candy, “Direct-feedback coders: design and performance with television signals,” IEEE Proc., vol. 57, pp. 776–786, May 1969.
[4] M. W. Hauser, P. J. Hurst, and R. W. Brodersen, “MOS ADC-filter combination that does not require precision analog components,” in ISSCC Dig. Tech. Paper, pp. 81–82, Feb. 1985.
[5] J. W. Scott, W. L. Lee, C. H. Giancarlo, and C. G. Sodini, “CMOS implementation of an immediately adaptive delta modulator,” IEEE J. Solid–State Circuits, vol. SC–21, pp. 1088–1095, Dec. 1986.
[6] C. H. Giancarlo, and C. G. Sodini, “A slope adaptive delta modulator for VLSI signal processing systems,” IEEE Trans. Circuits Syst., vol. CAS–33, pp. 51–58, Jan. 1986.
[7] S. K. Tewksbury, and R. W. Hallock, “Oversampled, linear predictive and noise-shaping coders of order N > 1,” IEEE Trans. Circuits Syst., vol. CAS–25, pp. 436–447, July 1978.
[8] W. L. Lee, and C. G. Sodini, “A topology for higher order interpolative coders,” in Proc. IEEE ISCAS’87, pp. 459–462, May 1987.
[9] J. C. Candy, and G. C. Temes, Oversampling Delta-Sigma Data Converters: Theory, Design, and Simulation, New York: IEEE Press, 1991.
[10] S. R. Norsworthy, R. Schreier, and G. C. Temes, Oversampling Delta-Sigma Data Converters: Theory, Design, and Simulation, New York: IEEE Press, 1997.
[11] K. C. Chao, and S. Nadeem, W. L. Lee, and C. G. Sodini, “A higher order topology for interpolative modulators for oversampling A/D converters,” IEEE Trans. Circuits Syst., vol. CAS–37, pp. 309–318, Mar. 1990.
[12] T. H. Kuo, K. C. Chen, and J. R. Chen, “Automatic coefficients design for high-order sigma-delta modulators,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 6–15, Jan. 1999.
[13] C. K. Ong, L. Siek, and L. S. Ng, “Minimum input sensitivity of high-order multi-stage sigma-delta modulator with first-order front-end,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 792–796, Aug. 2000.
[14] R. Schreier, “An empirical study of high-order single-bit delta-sigma modulators,” IEEE Trans. Circuits Syst. II, vol. 40, pp. 461–466, Aug. 1993.
[15] S. Jantzi, C. Ouslis, and A. Sedra, “Transfer function design for converters,” in Proc. IEEE ISCAS’94, pp. 433–436, May 1994.
[16] B. P. Agrawal, and K. Shenoi, “Design methodology for sigma-delta modulators,” IEEE Trans. Commun. vol. COM–31, pp. 360–369, Mar. 1983.
[17] E. F. Stikvoort, “Some remarks on the stability and performance of the noise shaper or sigma-delta modulators,” IEEE Trans. Commun. vol. 36, no. 10, pp. 1157–1162, Oct. 1988.
[18] B. P. Brandt, D. E. Wingard, and B. A. Wooley, “Second-order sigma-delta modulation for digital-audio signal acquisition,” IEEE J. Solid–State Circuits, vol. 26, no. 4, pp. 618–627, Apr. 1991.
[19] R. T. Baird, and T. S. Fiez, “Stability analysis of high-order delta-sigma modulation for ADC’s,” IEEE Trans. Circuits Syst. II, vol. 41, no. 1, pp. 59–62, Jan. 1994.
[20] W. B. Lin, T. H. Kuo, C. H. Su, and J. R. Chen, “Design and analysis of high order leapfrog topologies for sigma-delta A/D converters,” in Proc. IEEE APCCAS’94, pp. 10B.2.1–10B.2.6, Dec. 1994.
[21] W. B. Lin, and B. D. Liu, “The 4th-order leapfrog sigma-delta A/D converters stabilized by linear methodology,” Proc. 2001 International Symp. on Communications and Information Technology, pp. 283–286, Nov. 2001.
[22] S. M. Moussavi, and B. H. Leung, “High-order single-stage single-bit oversampling A/D converter stabilized with local feedback loops,” IEEE Trans. Circuits Syst. II, vol. 41, no. 1, pp. 19–25, Jan. 1994.
[23] R. Schaumann, M. S. Ghausi, and K. R. Laker, Design of Analog Filters, Englewood Cliffs, N. J.: Prentice Hall, 1981.
[24] P. F. Ferguson, Jr. A. Ganesan, and R. W. Adams, “One bit higher order sigma-delta A/D converters,” in Proc. IEEE ISCAS’90, pp. 890–893, May 1990.
[25] J. C. Candy, “A use of double integration in sigma delta modulation,” IEEE Trans. Commun. vol. COM–33, no. 3, pp. 249–258, Mar. 1985.
[26] B. E. Boser, B. A. Wooley, “The design of sigma-delta modulation analog-to-digital converters,” IEEE J. Solid–State Circuits, vol. 23, no. 6, pp. 1298–1308, Dec. 1988.
[27] L. R. Carley, “An oversampling analog-to-digital converter topology for high resolution signal acquisition systems,” IEEE Trans. Circuits Syst., vol. CAS–34, pp. 83–90, Jan. 1987.
[28] T. Ritoniemi, T. Karama, and H. Tenhunen, “The design of stable high order 1-bit sigma-delta modulators,” in Proc. IEEE ISCAS’90, pp. 3267–3270, May 1990.
[29] L. Brust and M. S. Tsay, “Mixing signals and voltages on chip,” IEEE Spectrum, vol. 30, pp. 40–43, Aug. 1993.
[30] M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, New York: IEEE Press, 1990.
[31] R. L. Geiger, P. E. Allen and N. R. Strader, VLSI Design Techniques for Analog and Digital Circuits, New York: McGraw–Hill, 1990.
[32] A. S. Sedra, and K. C. Smith, Microelectronic Circuits, 4th ed. New York: Oxford University Press, 1998.
[33] K. R. Laker, and W. M. C. Sanaen, Design of Integrated Circuits and Systems, New York: McGraw–Hill, 1994.
[34] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 2nd ed. New York: Oxford University Press, 2002.
[35] A. V. Oppenheim, and R. W. Schafer, Discrete-Time Signal Processing, Englewood Cliffs, N. J.: Prentice Hall, 1989.
[36] V. Manassewitsch, Frequency Synthesizer, Theory and Design, 2nd ed. New York: Wiely, 1989.
[37] H. T. Nicholas, and H. Samueli, “A 150 MHz direct digital frequency synthesizer in 1.25 m CMOS with –90 dBc spurious performance,” IEEE J. Solid–State Circuits, vol. 26, pp. 1959–1969, Dec. 1991.
[38] J. Tierney, C. M. Reder and B. Gold, “A digital frequency synthesizer,” IEEE Trans. Audio Electroacoust., vol. AU–19, pp. 48–57, 1971.
[39] H. T. Nicholas, III, H. Samueli, and B. Kim, “The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects,” in Proc. 42nd Annual Frequency Control Symp. USERA–COM (Ft. Monmouth, NJ.), pp. 357–363, May 1988.
[40] M. S. Lee and C. Chang, “Switched capacitor filters using the LDI and bilinear transformations,” IEEE Trans. Circuits Syst., vol. CAS–28, pp. 265–270, Apr. 1981.
[41] L. E. Turner and B. K. Ramesh, “Low sensitivity digital LDI ladder filters with Elliptic magnitude response,” IEEE Trans. Circuits Syst., vol. CAS–33, pp. 697–706, Jul. 1986.
[42] W. Chou, and R. M. Gray, “Dithering and its effects on sigma-delta and multi-stage sigma-delta modulation,” in Proc. IEEE ISCAS’90, pp. 368–371, May 1990.
[43] G. Zames, and N. A. Shneydor, “Dithering in nonlinear systems,” IEEE Trans. Automatic Control, 1976.
[44] L. Scuchman, “Dithering signals and their effects on quantization noise,” IEEE Trans. Acoustics Speech and Signal Processing, 1964.
[45] A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, New York: Wiley, 1984.
[46] Standford Telecom, Direct Digital Synthesizer Handbook, Santa Clara, CA, Mar. 1990.
[47] M. L. Blostein, “Sensitivity analysis of parasitic effects in resistance-terminated LC two-port,” IEEE Trans. Circuits Syst., vol. 14, pp. 21–25, Mar. 1967.
[48] L. T. Bluton, “Low sensitivity digital ladder filters,” IEEE Trans. Circuits Syst., vol. CAS-22, pp. 168–176, Mar. 1975.
[49] B. Nowrouzian, N. R. Bartley and L. Bruton, “Design and DSP–chip implementation of a novel bilinear–LDI digital Jaumann filter,” IEEE Trans. Circuits Syst., vol. CAS–37, No. 6, pp. 659–706, Jun. 1990.
[50] P. O’Leary and F. Maloberti, “A bit stream adder using oversampling,” Electron. Lett., pp. 1708–1709, Sep. 1994.
[51] R. E. Ziemer, and W. H. Tranter, Principles of Communications: systems, modulation, and noise, 4th ed. New York: John Wiley & Sons, 1995.
[52] A. K. Lu, and G. W. Roberts, “An analog multi-tone signal generator for built-in-self-test applications,” in Proc. 1994 International Test Conference, pp. 650–659, 1994.