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研究生： 楊孟法
Yang, Meng-Fa
論文名稱： 一個十位元每秒取樣二千七百萬次低功率逐漸趨近式類比數位轉換器
A 10-bit 27-MS/s Low Power SAR ADC
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 72
中文關鍵詞： 逐漸趨近式
外文關鍵詞： SAR ADC, successive-approximation
相關次數： 點閱：85  下載：24 
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    • 本論文研製了一個十位元操作在每秒二千七百萬次取樣頻率逐漸趨近似類比數位轉換器，採用了節省電容開關的切換機制，有效達到低功率消耗的目的。相較於傳統的切換方式，由電容陣列所組成的數位類比轉換器，其平均切換能量可減少81.3%。
    本設計的類比數位轉換器實現於TSMC 0.18-μm 1P6M互補金氧半製程，其核心電路面積為0.205 mm x 0.31 mm，整個晶片在1.8-V的供應電壓和27MS/s取樣頻率 ，消耗功率為1.21 mW，每次轉換所消耗的平均能量為 226.2 fJ。在20MS/s取樣頻率下，每次轉換所消耗的平均能量為 85.7 fJ。

    This thesis reports the design and implementation of a 10-bit 27-MS/s low-power successive-approximation-register (SAR) analog-to-digital converter (ADC). A set-and-down switching sequence technique is adopted to reduce the power consumption of the proposed ADC. The average switching energy of the capacitor array can be reduced by 81.3% compared to the conventional switching method.
    The designed ADC is fabricated in TSMC 0.18-μm 1P6M CMOS technology, and occupies 0.205 mm x 0.31 mm core areas. The total chip draws 1.21 mW from 1.8-V power supply at 27-MS/s sampling rate, and the average energy consumption per conversion step is 226.2 fJ. At 20-MS/s sampling rate, the average energy consumption per conversion step is 85.7 fJ.

    List of Figures VI List of Tables VIII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 Fundamentals of ADC 5 2.1 Ideal ADC 5 2.2 ADC Performance Metrics 7 2.2.1 Static Specifications 7 2.2.2 Dynamic Specifications 11 2.3 Review of ADC Architecture 16 2.3.1 Flash ADC 17 2.3.2 Pipelined ADC 18 2.3.3 Successive-Approximation (SAR) ADC 20 2.3.4 Summary of ADC Architectures 22 Chapter 3 The Principle of SAR ADC 24 3.1 The Architecture of SAR ADC 25 3.1.1 DAC-Based Successive Approximation 25 3.1.2 Charge-Redistribution ADC 27 3.2 Switching Method 31 3.2.1 Previous Switching Methods 31 3.2.2 Splitting Capacitor 37 3.2.3 Energy-Saving 39 Chapter 4 A 10-bit 27-MS/s Low Power SAR ADC 41 4.1 Motivation 41 4.2 ADC Architecture and Operation 42 4.2.1 Fully Differential 42 4.2.2 Set-and-Down 45 4.3 Circuit Implementation 49 4.3.1 Bootstrapped Switch 49 4.3.2 Comparator 52 4.3.3 DAC Capacitor Array 54 4.3.4 SAR Control Logic 56 4.4 Layout and Measurement setup 57 4.5 Measurement Result 60 4.6 Comparison and Discussion 66 Chapter 5 Conclusion and Future Work 68 Bibliography 70

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