本文主旨係針對交錯式SEPIC功因修正器進行分析與設計。SEPIC是一種可昇降壓且輸入與輸出電壓為同極性的轉換器，故適合作為功率因數修正電路之用。另外，本文將第一台開關信號作時間移位，以此作為第二台開關信號，以達到交錯式控制，並透過雙台並聯達到高輸出功率需求。本論文首先說明基本型SEPIC轉換器電路架構，再探討交錯型SEPIC轉換器電路架構，分析其電路動作原理及電路參數設計。最後實作一400 W交錯式SEPIC功因修正器，以驗證本架構之可行性與電路特性。

In this thesis, interleaved SEPIC ac-dc converters are analyzed and designed. Since the SEPIC converter provides a positive-polarity regulated output voltage with respect to the common terminal of the input voltage, the SEPIC converter applied as a power factor corrector become feasible. Interleaving control is achieved by the time-shift between two SEPIC converter to supply more power to the load. The topologies of typical and interleaved SEPIC are discussed, and the operating principles and design process are also studied in the thesis. Finally, a laboratory prototype of a 400 W interleaved SEPIC ac-dc converter is implemented to verify its feasibility and characteristics.

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