本論文提出適合影像應用的3.3伏，10位元，每秒135百萬次取樣速率類比數位轉換器。該轉換器是以摺疊及內插式的架構實現的，它被分成4位元以快閃式架構組成的粗調轉換器以及由摺疊級、內插級和比較級所組成的6位元微調轉換器。為了增加摺疊級的類比頻寬以及增益，在本專題中是採用了串接式的摺疊訊號。而且在架構上還使用了T/H來幫助系統穩定。在本專題中所使用的T/H並非傳統的Op-Amp形式的T/H，為了降低電路的複雜度，在這裡是採用分散式架構的T/H，而且利用平均電路的技術來降低分散式T/H之間的偏移電壓。

　　該ADC晶片是採用TSMC 0.18μm 1P6M CMOS的混合訊號製程來實現。在135百萬次取樣速率模擬下，給予頻率30MHz的正弦波輸入訊號可以得到將進10位元的解析度。整體晶片包含Pad的面積為1.96 mm2。輸出功率為148mW。

　This thesis describes a 3.3V, 10-bit, 135MS/s ADC suited for video applications. The proposed ADC is designed with a folding and interpolation architecture and is divided into two primary components, a 4-bit coarse converter and a 6-bit fine converter. The coarse converter is implemented by a full-flash architecture. And the fine converter is including three main blocks, a folding, an interpolation ,and a comparison stages. To increase the analog bandwidth and gain of the folding stage, a cascaded folding architecture is introduced to replace a conventional direct folding architecture. Furthermore, a T/H in front of the coarse and the fine converters is utilized to reduce the internal frequency produced by the folding processing circuits and the latency difference between the coarse and the fine converters. The T/H of the proposed ADC is implemented by distributed T/Hs in stead of a traditional single op-amp T/H. Besides, to decrease the offsets between the input stages of distributed T/Hs, an averaging technique is used and analyzed.

　The ADC is implemented by TSMC 1P6M 0.18um mixed-signal process. With a sinusoidal input signal with 30MHz frequency, it is verified to achieve 10-bit resolution at 135MS/s by SPECTRE simulation. The chip area including pads is 1.4 x 1.4mm2 and the power consumption is 148mW at 3.3V power supply.

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