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研究生: 蔡晏行
Tsai, Yen-Hsing
論文名稱: 一個應用於癲癇偵測與邊緣端訓練演算法之可程式化的RISC-V指令集深度學習加速硬體架構
A Programmable RISC-V DLA Hardware Architecture for Seizure Detection and On-device Training Algorithm
指導教授: 李順裕
Lee, Shuenn-Yuh
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2024
畢業學年度: 112
語文別: 中文
論文頁數: 121
中文關鍵詞: 生醫訊號處理癲癇偵測深度學習硬體加速RISC-V CPU邊緣端訓練
外文關鍵詞: Biosignal Processing, Seizure Detection, Deep Learning, Hardware Acceleration, RISC-V CPU, On-device Training
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  • 摘要 I 致謝 VIII 目錄 IX 表目錄 XI 圖目錄 XII 第一章 緒論 1 1.1 研究動機 1 1.2 研究背景 2 第二章 癲癇與資料庫 4 2.1 癲癇介紹與腦電圖 4 2.2 腦波數據資料庫 6 第三章 癲癇偵測演算法 8 3.1 演算法開發流程 8 3.2 訊號前處理演算法 10 3.2.1 離散小波轉換 11 3.2.2 標準分數正規化 12 3.3 人工智慧演算法 14 3.3.1 卷積類神經網路 14 3.3.2 模型訓練與架構設計 19 3.4 演算法壓縮與參數量化 28 3.4.1 演算法多層合併壓縮 28 3.4.2 參數量化 31 第四章 RISC-V指令集深度學習加速硬體架構 35 4.1 硬體架構與運作流程 35 4.2 控制器之實現 39 4.2.1 控制器的指令集 39 4.2.2 控制器的架構與狀態機 41 4.3 SPI之實現 44 4.4 RISC-V之實現 45 4.4.1 RISC-V的指令集 45 4.4.2 RISC-V的架構 48 4.5 DLA之實現 51 4.5.1 DLA的指令集 51 4.5.2 DLA的架構 52 第五章 演算法轉換與邊緣端訓練程式 59 5.1 演算法轉換 59 5.1.1 RISC-V程式 60 5.1.2 DLA程式 63 5.2 癲癇偵測程式 65 5.3 邊緣端訓練程式 72 第六章 系統實現與結果 80 6.1 演算法轉換器實作 81 6.2 硬體架構實作與模擬結果 84 6.3 Vivado電路實作與模擬結果 89 6.4 FPGA測試 90 6.5 系統實現結果 91 第七章 結論與未來展望 96 7.1 系統比較 97 7.2 未來展望 99 參考文獻 100 口試委員意見回覆 103

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