| 研究生: |
江振國 Chiang, Chen-Kuo |
|---|---|
| 論文名稱: |
應用於先進互補式金氧半技術原子層沉積(ALD)高介電常數閘極介電層之製作與特性研究 Fabrication and Characterization of High-k Gate Dielectrics Using Atomic Layer Deposition for Advanced CMOS Technology |
| 指導教授: |
王水進
Wang, Shui-Jinn |
| 學位類別: |
博士 Doctor |
| 系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
| 論文出版年: | 2012 |
| 畢業學年度: | 100 |
| 語文別: | 英文 |
| 論文頁數: | 170 |
| 中文關鍵詞: | 高介電質 、原子層沉積 、可靠度 、金氧半場效電晶體 、等效氧化層厚度 |
| 外文關鍵詞: | high-k dielectric, ALD, reliability, MOSFET, EOT |
| 相關次數: | 點閱:105 下載:4 |
| 分享至: |
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在半導體製程微縮的過程中,除了水平方向的縮減外,垂直方向也必須作等比例縮減來維持元件的基本操作。所以在45及32奈米時代,傳統的二氧化矽絕緣層厚度將需要縮小到約奈米左右,此時閘極之電子藉由穿隧(Tunneling)效應通過閘極氧化層流入元件之汲極,產生元件之大量漏電流及遷移率下降問題。為了降低閘極漏電流,必須將閘極絕緣層的實際厚度增加以減少穿隧電流,但是又要維持在電性操作時之等效氧化層厚度(Effective Oxide Thickness; EOT)不變。於是使用高介電常數(k)材料作為絕緣層,以同時兼顧閘極絕緣層實際厚度與電性等效厚度便成為眾所矚目之課題。尤其二氧化鉿(HfO2)於最近幾年為研究最廣之高介電材料。
氧化鉿可直接成長在矽晶片上擁有絕佳的熱穩定性、較高的介電係數、相對大的能隙寬度,但同時超薄氧化鉿面臨到了電子遷移率下降、大量的固定電荷、臨界電壓的不穩定等問題仍須解決,許多學者已證實透過添加材料(矽、鋁、氮、鈦、鉭)來改善氧化鉿所遭遇的問題,但必須考量到添加這些材料通常會降低氧化鋯的介電常數或者產生更大的漏電流。氧化鋯和氧化鉿有類似的化學結構,且能夠完全互溶。相較於氧化鉿,以二氧化鋯鉿當作閘極氧化層材料則擁有高電導,藉以降低電荷捕捉效應,獲得較高的驅動電流並改善N型金屬-氧化物-半導體的臨界電壓不穩的問題,以提升氧化值的品質和可靠度,如漏電流、磁滯、介面密度和優越的晶圓級厚度均勻性,在經過一連串的負壓測試,如溫度或大偏壓的情況下仍然能夠正常的運作。
Gate First製程在業界的發展比Gate Last製程早而且成熟,這使得Gate First製程有個好處,就是在積體電路設計和製程上不需改變太多步驟即可作業。但是對Gate First元件來說,不同程度的沉積會形成不同厚度的覆蓋層。這些沉積的覆蓋層可以改善漏電流的問題,但是越厚的覆蓋層會造成閘極介電層之中有更多的介面陷阱和氧空缺,進而造成更大的臨界電壓偏移。最大的關鍵在於,進入28奈米世代之後,Gate Last製程的元件電性將會比Gate First製程優良。
本論文主要在探討以原子層沈積法沈積高品質二氧化鋯鉿薄膜,藉由原子層沈積法的均勻性及高階梯覆蓋性,製作二氧化鋯鉿金氧半場效電晶體的閘極氧化層。此外,我們亦研究利用不同的氮化處理對於二氧化鋯鉿金氧半場效電晶體的等效氧化層厚度微縮能力的比較作討論。最後,我們研究以電漿氮化法(Decoupled Plasma Nitridation)不同製程參數調變時所處理的超薄氮化二氧化鋯鉿薄膜與元件的特性與均有深入的研究。論文第二章在ALD high-k薄膜製程中,比較使用不同種類的前導物(precursor)所製作的La2O3覆蓋層(capping layer)其材料物性特徵,與探討它們應用在nMOS的閘極優先型製程中,對於high-k介電閘極層MOS元件特性的影響。第三章研究ALD HfZrO2疊層中置入不同ZrO2位置的效應,並搭配La2O3覆蓋層在閘極優先或閘極後製的後續製程對於元件特性的比較。第四章研究ALD HfZrO2 介電層中的ZrO2 濃度效應與MOS元件可靠度的關係。第五章探討ALD HfZrO2經由氨氣熱氮化法(NH3 thermal nitridation)與去耦合電漿氮化(DPN)方式所製成的超薄氮化氧化鋯鉿(HfZrON)介電層的材料物性及其MOS元件等效氧化層厚度(EOT)縮微能力比較。第六章針對ALD HfZrO2的去耦合電漿氮化(DPN)製程,將電漿製程參數做最佳化調整,可有效地降低HfZrON的等效氧化層厚度,精確控制氮分佈測量圖,對於未來CMOS元件縮減厚度應用上具備絶佳的潛能。
In the downscaling process of the semiconductor industry , besides reduction in the horizontal direction, the basic operation that such proportions as the vertical direction must be done to reduce and maintain the properties of the component . Therefore , in 45 and 32 nm technology node , the thickness of the traditional insulator SiO2 will need to be reduced to about 1nm . However, the electrons of the gate can flow through gate oxide into drain by tunneling in this case, and produce large leakage current and thus the degradation of mobility . To decrease the leakage current, one must increase the physical thickness of the gate insulator to reduce the tunneling current, while keeping the EOT (equivalent oxide thickness) to maintain the characteristics of the devices. Using insulators with high dielectric constant is one of the attractive and popular method to research the problem. Among many candidate dielectric material, hafnium oxide (HfO2) has been extensively studied.
Hafnium oxide exhibits good thermodynamic stability on direct contact with Si , high dielectric constants, a large band offset with Si, suffers from mobility degradation, fixed charge and threshold voltage instability, etc.. The properties of HfO2 can be improved by adding different elements such as Si, Al, N, Ti ,Ta. It is reported that zirconium oxide (ZrO2) has similar chemical structure to that of HfO2 and is completely miscible in HfO2. HfZrO2 gate dielectric showed: higher trans-conductance. less charge trapping, higher drive current, lower NMOS Vt, reduced C-V hysteresis, lower interface state density, superior wafer-level thickness uniformity, and longer PBTI lifetime.
Gate first process was developed into manufacturing earlier than gate last. The fact leads to one of the advantages is that the integrated circuits design would not have to be changed so much for gate first. But for gate first devices, the various cycles of deposition would form various thicknesses of the capping layer. The deposition of capping layer could improve the leakage problems, but thicker capping layer of the gate first devices would induce more Dit and oxygen vacancies in gate dielectric. One important point is that the GL devices will have better characteristics than the GF ones while the fabrication process beyond 28nm technology node.
This research is to investigate the highly transparent HfZrO2 thin film used by Atomic Layer Deposition (ALD). Because of large area uniformity and high step coverage in fabricating MOSFET gate oxide application with the HfZrO2 films.。Besides, we study different nitridation treatment for the EOT scalability of ALD HfZrO2 MOSFETs application. Finally, we study the film and device characteristics of ALD HfZrON gate stack by tuning the process parameter of DPN as well. In the 2nd chapter, we studied the effects of the La2O3 capping layer interposed in Si/SiO2/HfO2/TiN high-k gate dielectric stacks prepared from two different ALD lanthanum precursors. In the chapter 3 and 4, we have systematically investigate hafnium zirconate (HfZrO2)/SiO2 MOSCAP device characteristics by changing the ZrO2 position and concentration in ALD HfO2 gate stack. In the chapter 5, NH3 thermal annealing and decoupled plasma nitridation (DPN) were employed for investigating the EOT scaling of HfZrO2. In the chapter 6, we compared the DPN and post nitridation anneal (PNA) processes for equivalent oxide thickness (EOT) scaling of ALD HfZrO2 gate dielectric. Finally, the Chapter 7 provides important conclusions and suggestion for future works worthy of further research.
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Chapter-6 References
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校內:2015-05-23公開