隨著第五代行動通訊(5G)技術的快速發展，穩定且低雜訊的頻率合成器成為無線高速系統中不可或缺的核心元件。傳統整數型鎖相迴路雖然能提供穩定的輸出，但其相位雜訊表現受限，難以滿足高速系統對訊號品質的嚴格要求。本論文採用次取樣鎖相迴路架構，以改善頻寬內相位雜訊。此架構最大的不同在於移除回授路徑上的除頻器，不僅消除除頻器本身的雜訊外，亦使相位偵測器與充電泵的雜訊傳遞至輸出端時不再被放大除頻器除數的平方倍，大幅改善頻寬內的相位雜訊。
然而，次取樣架構在運作過程中會引入二進制頻率偏移調變效應、電荷分享效應與電荷注入效應，導致參考突波惡化。為抑制上述效應，本論文在次取樣鎖相迴路中引入延遲鎖定迴路，以調整參考訊號的上升緣，使其對齊壓控振盪器之零交越點，進而有效降低電荷分享效應。除此之外，電路中亦加入緩衝器與虛擬取樣器，以進一步抑制二進制頻率偏移調變效應與電荷注入效應對壓控振盪器的干擾。
本設計採用TSMC 0.18µm CMOS製程，參考頻率為54.6875 MHz，輸出頻率為3.5 GHz。量測結果顯示，本設計可成功鎖定於目標頻率，並在啟動DLL後，參考突波由-55.55 dBc改善至-70.09 dBc，提升約14.5 dB。此外，在頻率偏移量為1MHz時的相位雜訊表現為-101.226 dBc/Hz，整體功率消耗為10.54 mW。

With the rapid advancement of fifth-generation mobile communication (5G) technology, stable and low-noise frequency synthesizers have become indispensable core components in high-speed wireless systems. Although conventional integer-N phase-locked loops can provide stable output frequency, their phase-noise performance is often insufficient to meet the stringent signal-quality requirements of modern high-speed communication systems. In this work, a sub-sampling phase-locked loop architecture is adopted to improve in-band phase noise. The key distinction of this architecture lies in the removal of the feedback divider, which not only eliminates the divider’s intrinsic noise but also prevents the noise generated by the phase detector and charge pump from being amplified by the square of the division ratio, thereby significantly enhancing the in-band phase-noise performance.
However, the sub-sampling architecture inherently introduces binary frequency-shift keying (BFSK) effects, charge-sharing effects, and charge-injection disturbances, all of which lead to reference-spur degradation. To suppress these effects, this work incorporates a delay-locked loop into the SSPLL to finely adjust the rising edge of the reference signal such that it aligns with the zero-crossing point of the voltage-controlled oscillator, effectively reducing charge-sharing interference. In addition, buffer stages and a virtual sampler are implemented to further mitigate BFSK and charge-injection effects on the VCO.
The proposed design is implemented in a TSMC 0.18-µm CMOS process, with a reference frequency of 54.6875 MHz and an output frequency of 3.5 GHz. Measurement results demonstrate that the loop successfully locks to the target frequency, and after enabling the DLL, the reference spur is improved from −55.55 dBc to −70.09 dBc, achieving an enhancement of approximately 14.5 dB. Furthermore, the measured phase noise is −101.226 dBc/Hz at a 1-MHz offset, and the total power consumption is 10.54 mW.

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