現今的嵌入式系統對於向量圖形的需求日漸增加，OpenVG是為硬體加速所制定之底層(low-level) 二維向量和點陣化(raster)繪圖的規格；它提供和儀器設備與廠商無關(device independent and vendor-neutral)的二維繪圖介面。相較於基於像素以及基於邊緣的繪圖架構，在有一條掃描線大小的繞線匝數緩衝器之基於掃描線的架構是比較合適於嵌入式系統。然而，傳統之基於掃描線的架構有下列的弊病，首先，為了支援全高清(Full HD)解析度(1920x1080)而使用的繞線匝數緩衝器，其面積對於像數位電視等的嵌入式系統而言還是太大。接著，對於存在外部記憶體的邊緣，如果橫跨了j條掃描線，就必須被讀取j次。
本篇論文主要著重在架構一個支援全高清解析度且有效率的點陣化單元。在OpenVG標準中，一張向量圖形由路徑(path)所組成，而路徑的寬度通常遠小於一條掃描線的寬度，這意味著當一條路徑被繪製時，在傳統基於掃描線之架構的繞線匝數緩衝器有大部分的空間未被使用，因此，本篇論文提出可擴充式及可重組的掃描線繪圖架構。這個架構在繪製那些寬度大於所採用之緩衝器的路徑時，會有可擴充式的特性，而且能讓點陣化單元只在限制框(bounding box)的範圍內運作，減少可擴充式的架構所造成之記憶體存取次數增加的代價。此外，當路徑寬度小於或等於所採用之緩衝器一半寬度時，這個架構會有重組化的特性，可以在從記憶體讀取一條邊緣後，同時執行多條的掃描線的點陣化運算，這樣可以減少記憶體存取次數。而邊界邊緣測試演算法也被應用於進一步降低繞線匝數運算的複雜度，在使用TSMC 0.13-μm CMOS製程合成並且操作頻率在200 MHz的情況下，本篇論文所提出的設計需要的等效邏輯閘數(gate count)為85k。在理想的匯流排延遲時間下的模擬結果顯示出本設計可以每秒繪製16.8張的解析度392x483的老虎測試圖。而本篇的論文架構也在包含ARM926EJ和賽林斯Spartan-3系列FPGA板的虹晶CDK平台上驗證。

Nowadays embedded systems have an increasing demand for vector graphics; OpenVG is a royal-free application programming interface (API) specified for two-dimensional vector and raster graphics. Compared to pixel-based and edge-based rendering architectures, scanline-based rendering architectures with scanline-size memory buffer are more suitable for embedded systems. However, conventional scanline-based architectures have the following drawbacks. First, the area for scanline-sized buffer for Full HD (19201080) is still too large for embedded systems like digital TV applications. Second, edges which are stored in the external memory cross j scanlines must be access j times.
This thesis focuses on the efficient rasteriztion implementation for Full HD. In OpenVG, a vector graphic consists of paths. The width of a path is generally much smaller than that of a scanline. This implies that much space in a scanline-sized buffer is not used in conventional scanline-based architectures when a path is drawn. Thus, a scalable and reconfigurable architecture for scanline-based rendering is presented. The proposed architecture has scalability for performing the drawing of the path of which the width is larger than that of the employed buffer. The memory access overhead is reduced for only performing rasterization in the range of the bounding box. Furthermore, when the width of a path is smaller than or equal to a half of that of the employed buffer size, the proposed architecture is reconfigurable for accessing an edge once and performing rasterization for multiple scanlines. This reduces memory access times. Boundary edge test algorithm is also employed for reducing the complexity of the winding number computation. Implementation results based on TSMC 0.13-m CMOS technology show that the proposed architecture operates at 200 MHz with 85K gates. Simulation result using ideal bus latency shows that the proposed design can render 16.8 (392483) Tiger images per second. The proposed design was also verified on the Socle CDK platform including ARM926EJ and Xilinx Spartan-3 series FPGA.

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