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研究生： 侯景文
Hou, Ching-Wen
論文名稱： 使用單一運算放大器並結合被動加法器於逐漸趨近式量化器之三階低失真三角積分調變器
Single-Opamp 3rd-order Low-Distortion Delta-Sigma Modulator with Merged Passive Adder SAR Quantizer
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 英文
論文頁數： 75
中文關鍵詞： 三角積分調變器 、放寬回授路徑技巧 、共享運算放大器技巧 、低失真架構
外文關鍵詞： Delta-sigma modulator, the relaxed feedback timing technique, opamp sharing technique, low-distortion topology
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    • 本論文提出一個適用於無線通訊應用之三角積分調變器。此三角積分調變器使用三階低失真的架構設計，以達到高解析度與低功率消耗之特性；另外並加入放寬回授路徑時間的技巧來延長量化器及動態元件匹配操作的時間，使得量化器可以採用慢速但低功耗的逐漸趨近式類比數位轉換器。本架構中，簡化了量化器前加總的路徑數及係數，使得額外的加法器可以使用結合了被動加法器的逐漸趨近式類比數位轉換器來完成，避免了額外的功率消耗。在電路實現方面，第一級與第二級的積分器共享運算放大器，且第二級積分器使用一個半週期延遲的雙重積分器，來更進一步地降低其功率消耗。此外，提出的三角積分調變器仍具有低失真的特性，且只使用一個運算放大器就能完成三階的三角積分調變器。
    此設計以台灣積體電路公司90奈米一層多晶矽九層金屬導線CMOS製程實現。模擬結果，在取樣頻率為60 MHz與超取樣率為16倍的設定下，噪訊比為79.01 dB且其整體功率消耗為2.85 mW，經換算此電路之功率轉換效率為0.104 pJ/conversion。晶片量測結果，取樣頻率40 MHz與超取樣頻率為16倍時，噪訊比為55.59 dB，功率總消耗為2.54 mW，功率轉換效率為1.984 pJ/conversion。

    In this thesis, a delta-sigma modulator suitable for wireless communication applications is proposed. The proposed delta-sigma modulator is designed in third-order low-distortion topology to achieve high-resolution and low-power consumption feature. In addition, the relaxed feedback timing technique is used to extend the processing time for quantizer and dynamic element matching (DEM) circuit. The low power consumption but low-to-medium speed successive-approximation (SAR) ADC can be chosen for the quantizer. In the proposed architecture, because of only two feedforward paths in front of the quantizer, the extra adder can be realized by a merged passive adder SAR quantizer which can avoid the extra power consumption. In circuit implementation, the opamp sharing technique is employed in the integrators between the first and second stage. Moreover, the second stage integrator is realized by double integrator to further reduce the power consumption. Besides, the feature of low-distortion DSM architecture still be preserved, and the third-order delta-sigma modulator is performed by only one opamp.
    This delta-sigma modulator is implemented by 90-nm 1P9M CMOS technology. The simulation results show that the peak SNDR is 79.01 dB with sampling frequency of 60 MHz and oversampling ratio (OSR) of 16. The power dissipation is 2.85 mW and the Figure-of-Merit (FoM) is 0.104 pJ/conversion. The measurement results show that the peak SNDR is 55.59 dB with sampling frequency of 40 MHz and OSR of 16. The power dissipation is 2.54 mW and the FoM is 1.984 pJ/conversion.

    Table of Contents Abstract (Chinese) i Abstract (English) iii Acknowledgement v Table of Contents vii List of Tables ix List of Figures xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 2 Chapter 2 Fundamental of Delta-Sigma Modulator 3 2.1 Introduction of Analog-to-Digital Converter 3 2.2 Delta-Sigma Modulator ADC 6 2.2.1 Oversampling feature 7 2.2.2 Noise-shaping feature 11 Chapter 3 Design of a Single-Opamp 3rd-order Low-Distortion Delta-Sigma Modulator 17 3.1 Architecture Consideration 18 3.1.1 Consideration of conventional structures 18 3.1.2 The low-distortion architecture 18 3.1.3 The low-distortion architecture with relaxed feedback timing 20 3.1.4 The multi-bit quantizer configuration 23 3.1.5 The opamp sharing technique 23 3.1.6 Double integrator 24 3.2 Proposed Delta-Sigma Architecture 25 3.2.1 Proposed architecture 25 3.2.2 Timing diagram 30 Chapter 4 Implementation in Circuit Level 33 4.1 Loop Filter Design 34 4.1.1 Switched-capacitor integrator 34 4.1.2 Opamp design 37 4.2 Quantizer design 42 4.2.1 4-bit SAR quantizer with passive adder 43 4.2.2 Capacitor DAC array 44 4.2.3 SAR logic 45 4.3 Data weighted averaging (DWA) design 48 4.3.1 Merged capacitor switching 49 4.3.2 DWA circuit design 50 4.4 Clock generator 54 4.5 Simulation results 56 4.6 Measurement results and discussion 61 Chapter 5 Conclusions and Future Work 67 5.1 Conclusions 67 5.2 Future Work 68 References 71

    [1] B. Razavi, Design of Analog Cmos Integrated Circuits. Boston. MA: McGraw-Hill, 2001, pp. 201–345.
    [2] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York: Oxford, 2011, pp. 613–729.
    [3] W. Sansen, Analog Design Essentials. Dordrecht, Netherlands: Springer, 2006, pp. 603–677.
    [4] T. Chan Carusone, D. Johns, and K. Martin, Analog Integrated Circuit Design. New York: J. Wiley & Sons, 2011, pp. 487–572.
    [5] F. Maloberti, Data Converters. Dordrecht, Netherlands: Springer, 2010, pp. 1–59.
    [6] J. M. de la Rosa and R. del Rio, CMOS Sigma-Delta Converters Praical Design Guide. New York: IEEE Press, 2013, pp. 1–30.
    [7] S. R. Norsworthy, R. Schreier, G. C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. New York: IEEE Press, 1997, pp. 1–41.
    [8] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. New York: IEEE Press, 2005, pp. 1–40.
    [9] K. Lee and G. C. Temes, "Improved low-distortion ΔΣ ADC topology," in Proc. IEEE Int. Symp. Circuits and Syst., May 2009, pp. 1341–1344.
    [10] J. Silva, U. K. Moon, J. Steensgaard, and G. C. Temes, "Wideband low-distortion delta-sigma ADC topology," Electron. Lett., vol. 37, pp. 737–738, Jun. 2001.
    [11] A. Gharbiya and D. A. Johns, "On the implementation of input-feedforward delta-sigma modulators," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, pp. 453–457, Jun. 2006.
    [12] J. Silva, U. K. Moon, and G. C. Temes, "Low-distortion delta-sigma topologies for MASH architectures," in Proc. IEEE Int. Symp. Circuits Syst., May 2004, pp. I-1144–7 Vol.1.
    [13] Y. L. Shen, “Design of a high-efficient delta-sigma modulator and simplified data weighted averaging algorithm, ” M.S. thesis, Dept. Elect. Eng., National Cheng Kung Univ., Tainan, Taiwan, R. O. C., 2012.
    [14] E. Bonizzoni, A. P. Perez, F. Maloberti, and G. C. Temes, "Third-order ΔΣ modulator with 61-dB SNR and 6-MHz bandwidth consuming 6 mW," in Proc. Eur. Solid-State Circuits Conf., Sept. 2008, pp.218–221.
    [15] I. J. Chao, C. L. Hsu, B. D. Liu, S. J. Chang, C. Y. Huang, and H. W. Ting, “A third-order low-distortion delta-sigma modulator with opamp sharing and relaxed feedback path timing,” IEICE Trans. Electron., vol. E95–C, pp. 1799–1809, Nov. 2012.
    [16] C. Lillebrekke, C. Wulff, and T. Ytterdal, ” Bootstrapped Switch In Low-Voltage Digital 90nm CMOS Technology,” in Proc. of the 23rd NORCHIP Conf., Nov. 2005, pp. 234–236.
    [17] M. Daliri, M. Maymandi-Nejad, and K. Mafinezhad, “Distortion analysis of bootstrap switch using Volterra series” IET Circ., Devices Syst., vol. 46, pp. 400–401, Dec. 2009.
    [18] M. Yavari and O. Shoaei, "A novel fully-differential class AB folded-cascode OTA for switched-capacitor applications," in Proc. IEEE Int. Conf. Electron. Circuits Syst., Dec. 2005, pp. 1–4.
    [19] M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei, "Pseudo-class-AB telescopic-cascode operational amplifier," Electron. Lett., vol. 40, pp. 219–221, Feb. 2004.
    [20] O. Choksi and L. R. Carley, "Analysis of switched-capacitor common-mode feedback circuit," IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 50, pp. 906–917, Dec. 2003.
    [21] Z. Chen, Y. Jiang, C. Cai, H. G. Wei, S. W. Sin, S. P. U, Z. Wang, and R. P. Martins, "A 22.4 uW 80dB SNDR sigma-delta modulator with passive analog adder and SAR quantizer for EMG application," in Proc. Asia Solid-State Circuits Conf., Nov. 2012, pp. 257–260.
    [22] G. Y. Huang, “Easily-integrated and energy-efficient design techniques for successive-approximation analog-to-digital converters, ” Ph.D. dissertation, Dept. Elect. Eng., National Cheng Kung Univ., Tainan, Taiwan, R. O. C., 2012.
    [23] R. T. Baird and T. S. Frez, “Improved delta-sigma DAC linearity using data weighted averaging,” in Proc. Int. Symp. Circuits Syst., May 1995, pp. 13–16.
    [24] S. M. Yoo, J. B. Park, S. H. Lee, and U. K. Moon, “A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 51, pp. 269–275, May 2004.
    [25] L. Bos, G. Vandersteen, P. Rombouts, A. Geis, A. Morgado, Y. Rolain, G. V. Plas, and J. Ryckaert, “Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1198–1208, Jun. 2010.
    [26] N. Maghari and U. Moon, "A third-order delta-sigma modulator using noise-shaped bi-directional single-slop quantizer," IEEE J. Solid-State Circuits, vol. 46, pp. 2882–2891, Dec. 2011.
    [27] O. Rajaee, S. Takeuchi, M. Aniya, K. Hamashita, and U. Moon, "Low-OSR over-ranging hybrid ADC incorporating noise-shaped two-step quantizer," IEEE J. Solid-State Circuits, vol. 46, pp. 2458–2468, Nov. 2011.
    [28] K. Yamamoto and A. C. Carusone, “A 1-1-1-1 MASH delta-sigma modulator with dynamic comparator-based OTAs,” IEEE J. Solid-State Circuits, vol. 47, pp. 1866–1883, Aug. 2012.
    [29] B. Murmann, "ADC performance survey 1997–2012," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.

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