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研究生：	吳翊豪 Wu, Yi-Hao
論文名稱：	支援位元率失真度最佳化之H.264畫面間預測架構設計 H.264 Inter Prediction Architecture Design with Rate-Distortion Optimization
指導教授：	陳中和 Chen, Chung-Ho
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	中文
論文頁數：	66
中文關鍵詞：	畫面間預測、多媒體處理器
外文關鍵詞：	inter prediction, media processor
相關次數：	點閱：90 下載：1
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H.264/AVC是由JVT所制定的新一代視訊壓縮標準，它加入許多新的視訊壓縮技術，例如變動區塊大小的位移補償、二分之一及四分之一像素取樣、位移向量預測、多重參考畫面等，使壓縮率及影像品質比以住的壓縮標準更好。但相對來說，更好的壓縮效率代表著編碼過程需要更多的資料計算以及記憶體存取，所以不只是即時性編碼的硬體實現難度更高，電力的消耗也會大幅增加。
在這篇論文中，我們針對H.264 baseline profile在影像編碼的部分，提出一個畫面間預測的硬體架構，支援H.264標準參考軟體所訂定的位元率失真度最佳化技術。論文中，針對大量資料計算及記憶體存取上做改進，在維持壓縮率及影像品質的前提下，希望能減低硬體上的電力消耗，並且使執行效率在可接受範圍內。最後，我們提出一個支援rate-distortion的inter prediction硬體架構設計，並且開發完成一個模擬H.264硬體架構設計的多執行緒軟體平台。

H.264/AVC is a new generation video coding standard developed by Joint Video Team (JVT). A number of new technical developments have been adopted to increase compression efficiency and video quality. These include improved inter prediction design features such as variable block-size motion compensation, half-pixel and quarter-pixel sampling, motion vector prediction, multiple reference frames, and etc. However, the high coding efficiency comes at the more computing capacity and memory access in a hardware design. It increases difficulty of hardware realization in real-time multimedia and low power consumption system.
This thesis proposes an architecture design of inter prediction of the H.264 baseline profile encoder. The design supports rate-distortion optimization in conformance with H.264 reference software. In this thesis, we aim to improve the computing capacity and memory access in the architecture design for reducing power consumption, and keep acceptable compression efficiency and video quality in real-time applications.

Chapter 1    Introduction    1
1    Motivation    1
2    Contribution of this thesis    3
3    Organization of this thesis    3
Chapter 2    Background    4
1    Overview of the H.264 standard    4
1.1    Variable block-size motion estimation    5
1.2    Motion vector prediction    6
1.3    Half-pixel and Quarter-pixel sampling    8
1.3.1    Luma half-pixel sampling    8
1.3.2    Luma quarter-pixel sampling    10
1.3.3    Chroma sub-pixel sampling    10
1.4    Rate-distortion optimization    11
1.4.1    Macroblock partitions prediction flow    11
1.4.2    Sub-macroblock partitions prediction flow    12
Chapter 3    Proposed Architecture    14
1    Inter prediction architecture design    14
1.1    Data computing capacity    15
1.2    Internal memory bandwidth    16
1.3    Rate-distortion optimization    17
2    Dual multi-cycle pipeline architecture    19
2.1    Current macroblock and reference window    20
2.2    Three stage multi-cycle pipeline    21
2.3    Macroblock prediction pipeline    22
2.4    Sub-macroblock prediction pipeline    23
3    Current macroblock and reference window    24
3.1    Current macroblock memory architecture    24
3.2    Reference window memory architecture    25
3.2.1    Two dimension interleaving 4×4 array memory    25
3.2.2    Two dimension address decoding and data reordering    27
3.3    Data pre-loading and supporting in pipeline    28
4    Look-ahead motion vector prediction    30
4.1    Macroblock prediction pipeline    31
4.2    Sub-Macroblock prediction pipeline    31
4.3    Look-ahead motion vector prediction    32
5    Luma integer-pixel motion estimation    35
5.1    Tri-point search algorithm    35
5.2    Tri-point search data reuse    37
5.3    Tri-point search architecture    39
6    Luma sub-pixel motion estimation    43
6.1    Two step closed search algorithm    43
6.2    Two step closed search architecture    46
Chapter 4    Simulation and Verification    49
1    Software simulation    49
2    Software/Hardware co-verification    51
Chapter 5    Experimental Results    52
1    Integer-pixel motion estimation    52
1.1    Search points in different sequence    52
1.2    Average PSNR and PSNR difference from FS    53
1.3    Average bitrate and bitrate difference ratio to FS    54
1.4    PSNR-bitrate comparison in different sequence    55
2    Sub-pixel motion estimation    57
2.1    Search points in different sequence    57
2.2    Average PSNR and PSNR difference from 2SFS    58
2.3    Average bitrate and bitrate difference ratio to 2SFS    59
2.4    PSNR-bitrate comparison in different sequence    60
3    Dual multi-cycle pipeline architecture    61
3.1    Average PSNR and PSNR difference from SW    61
3.2    Average bitrate and bitrate difference ratio to SW    62
3.3    PSNR-bitrate comparison    63
Chapter 6    Conclusion    64
                                    

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[2] Joint Video Team Reference Software JM 7.3, http://iphome.hhi.de/suehring/tml/download/, Aug. 2003.
[3] T. Wiegand, G. J. Sullivan, G. Gjontegaard, and A. Luthra, “Overview of the H.264/AVC video coding Standard,” IEEE Transaction on Circuits and Systems on Video Technology., Volume 13, Pages 560-576, Jul. 2003.
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校內：2007-09-15公開
校外：2007-09-15公開

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