| 研究生: |
黃惠敏 Huang, Hui-Min |
|---|---|
| 論文名稱: |
應用於Ka頻帶之次諧波混頻器設計 Design of Sub-Harmonic Mixers for Ka-Band Application |
| 指導教授: |
許渭州
Hsu, Wei-Chou |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
| 論文出版年: | 2007 |
| 畢業學年度: | 95 |
| 語文別: | 英文 |
| 論文頁數: | 61 |
| 中文關鍵詞: | 主動式次諧波混頻器 、反並聯式配對二極體 、單石微波積體電路 、次諧波混頻器 |
| 外文關鍵詞: | APDP, sub-harmonic mixer, MMIC, active sub-harmonic mixer |
| 相關次數: | 點閱:81 下載:4 |
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在本論文中,我們提出了兩種應用於Ka頻段,不同架構之次諧波降頻混頻器。並透過國家晶片中心(CIC),利用WIN 0.15UM PHEMT製程以單石微波積體電路來實現。
在第一種架構之次諧波混頻器中,我們利用反並聯式配對二極體對基頻混頻訊號的抑制特性,來做為次諧波混頻器之基本組件。將四對反並聯式配對二極體接成環狀結構,並藉由兩組藍格偶合器將射頻及本地震盪源訊號功率等分成相差90度之訊號,饋入環狀結構。如此之架構,在射頻頻率由26至38 GHz的頻段內皆有良好之射頻及本地震盪源對中頻隔離度,其隔離度分別大於25及19 dB。而其轉頻損耗也都小於17 dB (此為實際量測結果),在34至38 GHz間轉頻損耗甚至可小於15 dB,為一寬頻之次諧波混頻器。
在第二種架構中,我們則是利用FET來實現主動式次諧波混頻器。此為串疊結構之次諧波混頻器,在轉頻損耗及消耗功率的取捨下,我們選擇消耗功率為21.2毫瓦,射頻頻率由28.5至30.4 GHz的頻段內其轉頻損耗皆小於6 dB,射頻及本地震盪源對中頻隔離度分別為大於42及12 dB (此為模擬結果),為一較為窄頻之次諧波混頻器。
比較此二不同架構之次諧波混頻器,可知被動式(二極體)之次諧波混頻器可以得到較大的頻寬,而主動式次諧波混頻器則可達到較佳之轉頻損耗。無論是主動式或被動式皆有其優缺點,其選擇則視所應用之需求而定。
We have proposed two novel structures of sub-harmonic down-conversion mixers for Ka band application in this thesis. Through National Chip Implementation Center (CIC), the circuits are implemented in form of monolithic microwave integrated circuit (MMIC) by the WIN 0.15UM PHEMT process.
In the first mixer structure, we take the advantage of the fundamental mixing suppression of the anti-parallel diode pair (APDP), and use it as the basic unit in the proposed sub-harmonic mixer. Four pairs of anti-parallel diodes are connected in a ring form. Both the RF and LO signals are divided to two half power signals with 90o phase difference by Lange couplers, and fed to the ring structure. The measured result shows that this structure has good RF/LO to IF isolations. The RF/LO to IF isolations are more than 25 and 19 dB from 26 to 38 GHz. The conversion loss is less than 17 dB in the same range. (In the range from 34 to 38 GHz, the conversion loss is less than 15 dB.) It is a broad band mixer.
The FETs are applied to implement the active sub-harmonic mixer, in the second structure. Two FETs are connected in a cascode topology. It is a trade off between the conversion loss and power consumption. The power consumption is chosen to be 21.2 mW, and the conversion loss is less than 6 dB from 28.5 to 30.4 GHz in simulation. The RF/LO to IF isolations are more than 42 and 12 dB. It is a narrow band mixer.
Comparing these two sub-harmonic mixers, we can get that the passive (diode) sub-harmonic mixer is broader band, while the conversion loss is better in the active sub-harmonic mixer. The choice between the passive and active sub-harmonic mixers depends on the applied requirement.
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