隨著超大型積體電路（VLSI）技術的迅速發展，電路的複雜度與運作速度大幅提升，使得電路測試面臨更嚴峻的挑戰。同時，測試回應中的未知值（X-values）也日益增加，嚴重影響測試品質與準確性。本文提出一種新穎的未知值遮罩（X-masking）技術，能在維持高測試品質的同時，有效降低面積開銷與測試資料量。我們所提出的高效未知值遮罩架構，結合了掃描鍊分組與掃描鍊分區技術，能完整過濾未知值，並提升可觀察性。此外，本文設計了一種測試向量模式單元，有效減少測試向量中額外控制位元所帶來的開銷。多組基準電路的實驗結果顯示，本文所提方案在測試資料量、測試覆蓋率以及面積開銷方面均優於現有技術。

The rapid advancements in VLSI technology have led to increased circuit complexity and speeds, making circuit testing significantly challenging. Additionally, the number of unknown values (X) has increased, which may severely degrade test quality and accuracy. This paper proposes a novel X-masking scheme that achieves high test quality with low area overhead and reduced test data volume. An efficient X-masking architecture together with novel scan grouping and scan chain partitioning successfully filter out unknown values completely while enhancing observability. Furthermore, a pattern mode unit is designed to effectively reduce the overhead of additional control bits in test patterns. Experimental results demonstrate that the proposed scheme outperforms existing techniques regarding test data volume, test coverage, and area overhead.

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