本論文主要針對可調變頻率與電壓之多核心晶片之平面規劃進行探討。為了達到低功耗的目標，本文中的晶片使用多重電壓源的方法來動態調節效能，由於多重電壓源的架構，增加了平面規劃與電源線規劃的困難度，除此之外，為了使得溫度感測器，可以確實感測到相關模組的溫度，必須將其擺放在適當的位置，這也使得實體設計的複雜度變得越來越高。為了考量多重供應電壓源的電源線規劃，在這篇論文中我們使用了電壓島的平面佈局規劃，並且為了使得晶片可以達到更佳的效能，我們根據平面規劃的結果去調整IO單元的相關擺放位置。本篇論文採用階層式架構去降低實體設計的複雜度，首先，在晶片層級時考量電壓島的平面規劃，將操作在相同電壓的模組集合在一起，以便利之後的多重電壓源規劃，並且同時調整電源相關的IO單元擺置位置。接著，進入模組層級規劃，為了使得溫度感測器可以感測到相關的模組並且同時考量效能，我們在各模組中找出最適當擺放溫度感測器的位置，並且進行最佳化擺置與繞線流程。最後，再回到晶片層級，重新調整IO單元的位置，使得它們可以擺放於相關的模組旁邊，以提升晶片的效能，並且根據平面規劃的結果來完成電源線規劃。

This thesis mainly focuses on the floorplanning for a multi-core design, whose frequency and voltage can be adjusted. In order to reduce power consumption, Multiple Supply Voltage (MSV) technique is adopted in the chip, which increases the difficulties in floorplanning and powerplanning. Besides, to enable temperature sensors to detect temperatures of associated modules precisely, they must be placed at appropriate locations inside a block, which makes physical design a tough task. To consider powerplanning for MSV, voltage island-driven floorplanning is adopted in our methodology and relative locations of IO Pads have to be adjusted according to the resulting floorplan to ensure performance of a chip. We adopt hierarchical design flow to reduce the complexity in physical design. First stage is chip-level floorplanning considering voltage islands, in which modules operated at the same voltage are clustered together to facilitate powerplanning in later stages. Moreover, the locations of power-related IO pads are adjusted at the same time. Next stage is block-level floorplanning stage. Locations of temperature sensors in a block are determined such that they can detect temperatures of associated modules without violating timing in the block. Then, placement and routing are completed. Finally, it comes back to chip-level floorplaning. To improve performance of a chip, locations of IO Pads are adjusted according to resulting floorplan to make them can be placed close to relevant modules and powerplanning is completed.

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