由於積體電路複雜度的急劇上升，測試大型業界電路設計所需的測試數據量和測試應用時間以非常快的速度增加。在過去的二十年中，電路晶片上測試壓縮硬體已成為一種實用的技術，這個技術可以被用於大幅降低總體測試成本。如何決定測試壓縮硬體的最佳輸入通道數和最佳輸出通道數以致最小之測試數據量並同時維持可接受之測試覆蓋率是一個需要處理的問題。在本論文中，開發了一種有效的方法來估計輸入和輸出通道數對測試資料量和測試配置的測試覆蓋率的影響。然後可以將估計結果用於確定每種配置的測試數據量，因此可以預測具有最低測試數據量的測試壓縮配置，而不會降低測試覆蓋率。當將設計嵌入到SoC系統中時，設計的每個配置上的測試資料量結果也可以用於確定最合適的配置。

Test data volume and test application time required to test large industrial designs ramp up rapidly due to the drastic increase in circuit complexity. Over the past two decades on-chip test compression hardware has become a pragmatic technology to cut down the overall test costs. How to determine the optimal input and output channel counts for test compression hardware that results in minimum test data volume with acceptable test coverage is a critical issue. In this thesis efficient methods to estimate the impact of both input and output channel counts on test pattern counts and test coverages of test configurations are developed. The estimation results can then be utilized to determine the test data volume for each configuration and thus the test compression configuration with the lowest test data volume without degrading the test coverage can be predicted. The pattern count results on each configuration of a design can also be used to determine the best suitable configuration when the design is to be embedded in a SoC system.

[1] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, 2006.
[2] N.A. Touba, “Survey of test vector compression techniques,” IEEE Design & Test of Computers, vol. 23, pp. 294-303, 2006.
[3] R. Kapur, S. Mitra, and T.W. Williams, “Historical perspective on scan compression,” IEEE Design & Test, vol. 25, no. 2, pp. 114-120, 2008.
[4] K-J. Lee, J-J. Chen, and C-H. Huang, “Using a single input to support multiple scan chains,” Proc. ICCAD, pp. 74-78, 1998.
[5] L.-T. Wang, X. Wen, S. Wu, Z. Wang, Z. Jiang, B. Sheu, and X. Gu, “VirtualScan: test compression technology using combinational logic and one-pass ATPG,” IEEE Design & Test, vol. 25, no. 2, pp. 122-130, 2008.
[6] A. Chandra, R. Kapur and Y. Kanzawa, “Scalable Adaptive Scan (SAS),” Proc. DATE, pp. 1476-1481, 2009.
[7] B. Koenemann, “LFSR-coded test patterns for scan designs,” Proc. ETC, pp. 237-242, 1991.
[8] J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, N. Tamarapalli, and J. Qian, “Embedded deterministic test for low cost manufacturing,” IEEE Design & Test, vol. 20, pp. 58-66, 2003.
[9] J. Rajski, M. Kassab, N. Mukherjeek, J. Tyszer, “Method and Apparatus for Selectively Compacting Test Responses,” US Patent 7,805,649.
[10] C.-H. Wu, Y. Huang, K.-J. Lee, W.-T. Cheng, G. Veda, S. Reddy, C.-C. Hu, C.-S. Ye, “Deep Learning Based Test Compression Analyzer,” Proc. ATS, 2019.
[11] F.-J. Tsai, C.-S. Ye, Y. Huang, S.-X. Zheng, K.-J. Lee, W.-T. Cheng, S. M. Reddy, M. Kassab, and J. Rajski, “Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channel,” Proc. ITC-Asia, pp. 130-135, 2020.
[12] M. Kassab, G. Mrugalski, N. Mukherjee, J. Rajski, J. Janicki, J. Tyszer, “Dynamic Channel Allocation for Higher EDT Compression in SoC Designs,” Proc. ITC, 2010.
[13] J. Janicki, J. Tyszer, A. Dutta, M. Kassab, G. Mrugalski, N. Mukherjee, J. Rajski, “EDT Channel Bandwidth Management in SoC Designs with Pattern-Independent Test Access Mechanism,” Proc. ITC, 2011.
[14] J. Rajski, J. Tyszer, G. Mrugalski, W.-T. Cheng, N. Mukherjee, M. Kassab, “X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector,” IEEE Trans. on CAD of Inte. Circ. and Syst., pp. 147-159, 2008.
[15] F.-J. Tsai, C.-S. Ye, K.-J. Lee, S.-X. Zheng, Y. Huang, W.-T. Cheng, S. M. Reddy, M. Kassab, J. Rajski, Chen Wang, and Justyna Zawada, “ Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations,” Proc. ITC, 2020.