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研究生： 郭建忠
Kuo, Chien-Chung
論文名稱： 應用於H.264中低功率架構CABAC編碼器的設計
Design of a Low Power Architecture for CABAC Encoder in H.264
指導教授： 雷曉方
Lei, Sheau-Fang
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2006
畢業學年度： 94
語文別： 英文
論文頁數： 86
中文關鍵詞： 條件化可調性二位元算術解碼器 、可變長度標籤的快取記憶體
外文關鍵詞： variable length tag cache memory, context based adaptive binary arithmetic coding
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    • 在這篇論文當中，我們實現了一個應用於H.264裡低功率架構的條件化可調性二位元算術解碼器(CABAC)。在CABAC裡面為了要有更高的壓縮效率，必須對最有可能出現的符號(MPS)要有精準的機率估測值。針對硬體設計而言，這樣的動作就表示要重複的更新儲存在記憶體裡面的機率估測值。因此為了要減少執行算術編碼時的功率消耗，階層式的記憶體觀念以及適當的架構是非常重要的準則。基於之前所敘述的功率消耗的考量，我們提出了一個可變長度標籤的快取記憶體以及管線式的架構來完成我們的硬體設計。
    模擬結果證實我們所提出的架構可以達到50%功率消耗的節省，另外我們的編碼速率也可以達到每秒200M個符號。最後我們在Creator的驗證平台上針對我們設計的硬體來完成軟硬體共同模擬的動作。

    In this thesis, we propose a low power architecture for the implementation of context based adaptive binary arithmetic coding (CABAC) system in H.264. CABAC needs to have the accurate probability estimations for most probable symbol (MPS) to enhance higher compression ratio. This data compression efficiency can be implicitly achieved by iteratively updating probability models stored in the embedded memory for hardware design. Therefore the design of the memory hierarchy and the suitable architecture is an important issue so that the power consumption can be kept low caused by memory accesses for iteratively executing arithmetic coding operations. To address the low power consideration for designing a CABAC encoder, we propose the architecture by using variable length tag cache memory scheme and pipeline structure.

    The simulation results show that our proposed architecture can achieve 50% power consumption saving, and throughput can be higher than 200Mbps. Finally, we also verify our design with SW / HW co-simulation environment on the Creator verification platform.

    摘要 i ABSTRACT ii ACKNOWLEDGEMENT iii OUTLINE iv LIST OF TABLES vi LIST OF FIGURES vii CHAPTER 1 - INTRODUCTION 1 1.1. Motivation 1 1.2. Entropy Coding 3 1.2.1. Context-Based Adaptive Variable Length Coding（CAVLC） 3 1.2.2. Context-Based Adaptive Binary Arithmetic Coding（CABAC） 4 1.3. Literature Survey & Compared 5 1.4. Introduction to Proposed Architecture 6 1.5. Organized 7 CHAPTER 2 – REVIEW OF CABAC SYSTEM 9 2.1. Overview of CABAC 9 2.2. Binarization 10 2.2.1. Binarization Process for Macroblock Type 10 2.2.2. Binarization Process for Level Information 12 2.3. Context Modeling 15 2.3.2. Initialization Process for Context (ctx) Variables 16 2.3.3. Derivation Process of Context (ctx) for the Syntax Element - mb_skip_flag 25 2.3.4. Derivation Process of Context (ctx) for the Syntax Element - Coding Procedure of Residual Coefficient 26 2.4. Binary Arithmetic Coding 29 2.4.4. Probability Estimation Modeling 29 2.4.5. Arithmetic Operation 31 2.4.6. Renormalization Loop 33 CHAPTER 3 – PROPOSED ARCHITECTURE 35 3.1. Overview of Pipeline Scheme 35 3.2. Update Stage 35 3.2.1. Power Measurement for Different Memory Size 36 3.2.2. Cache Memory Design Methodology 37 3.2.3. Design of Variable-Length Tag Cache Memory 40 3.2.4. Improvement of Compare Circuit for Cache Memory 41 3.2.5. Update Stage Hardware Architecture 43 3.3. Range/Low Stage 44 3.4. BO Stage 45 3.4.1. BO Stage Design Methodology 47 3.4.2. BO Stage Hardware Architecture 49 3.5. Pipeline Scheme Synthesis Diagram 50 CHAPTER 4 – EXPERIMENT RESULT 52 4.1. Measurement Result for Hit Ratio 53 4.2. Reducing of Hardware Complexity and Power Consumption Measurement 54 CHAPTER 5 – SIMULATION RESULT & VERIFICATION ENVIROMENT 63 5.1. HW / SW Implementation 63 5.2. Introduction to ARM Architecture 64 5.3. Introduction to FPGA Architecture 66 5.4. Memory Map IO 66 5.5. FPGA Wrapper Design Methodology 67 5.6. Simulation Result 72 5.7. Area Analysis 80 5.8. Timing Analysis 81 CHAPTER 6 – CONCLUSIONS AND FUTURE WORKS 82 REFERENCE 84 作者簡歷 86

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