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研究生: 黃俊維
Huang, Chun-Wei
論文名稱: 二硫化鉬/石墨烯異質結構之電晶體應用
MoS2/Graphene Hetero-structures for Transistor Applications
指導教授: 張守進
Chang, Shoou-Jinn
共同指導教授: 林時彥
Lin, Shih-Yen
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2021
畢業學年度: 109
語文別: 中文
論文頁數: 82
中文關鍵詞: 石墨烯二硫化鉬二維材料異質結構上閘極式電晶體平面式閘極電晶體
外文關鍵詞: Graphene, Molybdenum Disulfide, Hetero-structures, In-Plane Gate Transistors, Top-gate field effect transistor
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  • 本論文中我們以石墨烯薄膜作為場效電晶體元件的薄膜作為主軸,利用乙烷 ( ethane, C2H6 ) 以化學氣相沉積技術在藍寶石基板上成長大面積的石墨烯薄膜,運用乙烷的解離能小於甲烷 ( methane, CH4 ) 的特性,使得碳的裂解情況比常見的甲烷更有效率,藉由調整成長壓力和時間來優化薄膜,再製作成上閘極結構以及平面式閘極結構來展示石墨烯薄膜之特性。由於在上閘極電晶體的結構裡必須要成長氧化層來隔絕閘極,但二維材料和氧化層的介面問題導致電晶體特性不理想,在氧化層中會有許多缺陷使得漏電流變大,元件容易穿透氧化層使元件崩潰,我們更改電晶體結構成平面式閘極,在平面式閘極電晶體中,汲極、源極和閘極皆位在同一平面上,此結構不需要氧化層來隔絕閘極和薄膜,解決了氧化層和二維材料之間的介面問題。在平面閘極電晶體的製程裡,運用電子束微影技術 ( EBL ) 使其元件尺寸可以更小,進而達到更好的電特性。在討論完石墨烯薄膜的各式電晶體結構後,在石墨烯薄膜上成長二硫化鉬作為保護層,避免在製程的中造成石墨烯薄膜的破壞以及其他製程步驟對通道薄膜的汙染,進而探討其元件特性,二硫化鉬的成長方式分別為濺鍍成長、熱蒸鍍成長。在石墨烯上濺鍍成長二硫化鉬,因為電漿射頻系統對於石墨烯薄膜的破壞導致無法成膜;因此我們選用熱蒸鍍的方法來成長二硫化鉬,在元件製備過程中,利用原子層蝕刻技術,將金屬電極底下作為保護層的的二硫化鉬蝕刻掉,之後再進行後續製程,發現載子遷移率可以有效的提升。

    In this thesis, we have fabricated transistors with top and in-plane gates on bi-layer graphene films grown directly on sapphire substrates [1] by using photo-lithography and e-beam lithography, respectively. For top-gate graphene transistors, since there are no dangling bonds on graphene surfaces, it is difficult to achieve uniform precursor distribution on the graphene surface for the growth of dielectric layer by using the atomic layer deposition. In this case, the inferior dielectric layer would lead to a high leakage current and therefore, the breakdown of the device. On the other hand, since the channel is only of bi-layer graphene, strong carrier scatterings are observed on the Al2O3/graphene interface, which will degrade the field-effect mobilities of the top-gate graphene transistors. To avoid the influence of the dielectric layer to the graphene channel, graphene transistors with in-plane gates are fabricated. Since there is no dielectric layer for this device, compared with top-gate graphene transistors, significant field-effect mobility enhancement is observed for the device with in-plane gates. However, for this device architecture, the graphene channel is exposed to the atmospheric environment, we have deposited another MoS2 layer on top of the graphene channel by using the thermal evaporation. An even higher field-effect mobility value is observed for the MoS2-passivated graphene transistor with in-plane gates after the removal of MoS2 films underneath the source/drain electrodes. Besides the field-effect mobility enhancement, we have also observed large Dirac point shift under light irradiation, which suggests that the MoS2-passivated graphene transistor with in-plane gates can also act as a high-speed photo-transistors.

    目錄 摘要 i Abstract ii 致謝 vii 目錄 ix 表目錄 xiii 圖目錄 xiv 第一章 緒論 1 1-1 研究動機與論文架構 1 1-2 二硫化鉬的基本特性 2 1-2-1 二硫化鉬的晶體結構與特性 2 1-2-2 二硫化鉬的拉曼光譜特性 3 1-2-3 二硫化鉬之製備方式 3 1-2-4 二硫化鉬之光激發螢光光譜分析 5 1-3 石墨烯的基本特性 5 1-3-1 石墨烯的晶體結構與特性 5 1-3-2 石墨烯的拉曼光譜及霍爾量測 6 1-3-3 石墨烯的製備方式 8 i. 機械剝離法 ( Mechanical Exdoliation ): 8 ii. 磊晶成長法 ( Epitaxial Growth ) 8 iii. 氧化還原法 ( Reduction from Graphene Oxides ): 9 iv. 化學氣相沉積法 ( Chemical Vapor Deposition ): 9 第二章 實驗原理與實驗儀器 18 2-1 材料成長系統 18 2-1-1 射頻濺鍍系統 ( Sputtering system ) 18 2-1-2 真空高溫硫化系統 19 2-1-3 熱蒸鍍沉積系統 ( Thermal evaporation ) 20 2-1-4 原子層沉積系統 ( ALD system ) 21 2-1-5 低壓化學氣相沉積系統 ( Low pressure Chemical vapor deposition ) 22 2-2 材料分析儀器&材料電性量測儀器 23 2-2-1 拉曼光譜儀 23 2-2-2 掃描式電子顯微鏡 ( Scanning Electron Microscopy ) 24 2-2-3 霍爾量測系統 ( Hall measurement ) 25 2-2-4 光激螢光光譜儀 26 2-3 電晶體元件製程設備 27 2-3-1 熱蒸鍍系統 ( Thermal evaporation system ) 27 2-3-2 原子層沉積系統 ( Atoms Layer Deposition system ) 28 2-3-3 反應式離子蝕刻系統 28 2-3-4 電子束真空蒸鍍系統 29 2-3-5 原子層蝕刻系統 ( ALE, Atomic layer etching ) 29 2-3-6 電子束顯影系統 ( Electron-Beam lithography ) 30 2-3-7 電晶體元件三端點量測系統 31 第三章 石墨烯薄膜及其異質結構之上閘極場效電晶體 40 3-1 石墨烯基板之薄膜製備 40 3-2 石墨烯之上閘極場效電晶體製備及量測 42 3-2-1 定義源極和汲極 ( Source & Drain region definition ) 44 3-2-2 定義通道區域 ( Channel region definition ) 46 3-2-3 氧化層沉積 ( Oxide layer deposition ) 47 3-2-4 定義閘極 ( Gate region definition ) 47 3-2-5 元件測量 ( Transistor measurement ) 48 3-3 異質結構二硫化鉬/石墨烯之上閘極場效電晶體 49 3-4 結論 50 第四章 石墨烯與異質結構薄膜及其平面式閘極場效電晶體 52 4-1 石墨烯之平面閘極場效電晶體 52 4-1-1 定義源極、汲極和閘極 ( Source & drain and gate region definition ) 53 4-1-2 定義延伸電極 ( Extend contact metal definition ) 53 4-1-3 定義通道區域 ( Channel region definition ) 56 4-1-4 元件測量 58 4-1-5 石墨烯薄膜之平面閘極場效電晶體的遲滯現象以及光電流效應 61 4-2 二硫化鉬的製備以及比較 62 4-2-1 石墨烯上濺鍍成長三氧化鉬 63 4-2-2 石墨烯上熱蒸鍍成長三氧化鉬 64 4-3 二硫化鉬/石墨烯薄膜及其平面閘極場效電晶體 66 4-3-1 二硫化鉬/石墨烯薄膜平面閘極電晶體製備與特性 66 4-3-2 二硫化鉬/石墨烯薄膜平面閘極電晶體的遲滯現象 ( Hysteresis ) 67 4-3-3 二硫化鉬/石墨烯薄膜平面閘極電晶體的光電流反應 69 4-3-4 二硫化鉬/石墨烯經原子層蝕刻 ( ALE ) 後製作成平面閘極元件 70 4-4 結論 74 第五章 總結 75 5-1 總結 75 5-2 未來展望 77 參考文獻 78

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