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研究生： 張正道
Chang, Jeng-Dau
論文名稱： 十位元350MHz電流導向數位類比轉換器
10-bit 350-MSample/s Current-Steering Digital-to-Analog Converter
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2004
畢業學年度： 92
語文別： 英文
論文頁數： 73
中文關鍵詞： 數位類比轉換器 、電流導向
外文關鍵詞： DAC, Current-Steering
相關次數： 點閱：70  下載：6 
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    • 　　本論文中，我們利用標準數位CMOS製程去探討、實現一個電流導向350 MHz數位類比轉換器。將數位類比轉換器的輸入設計為六個最大位元轉換成溫度碼、四個最小位元使用二進位碼，並選擇適當的電流源電晶體面積去克服因製程變動所造成之元件不匹配的問題。在電流單元的設計上，我們採用疊加開關的架構去提升數位類比轉換器性能，譬如INL和SNDR的特性。此外也設計一個高速且具高切換點的切換開關去減低在訊號切換過程中所造成的瞬時脈衝的錯誤。
    　　模擬的結果顯示出INL小於±0.2 LSB而DNL在±0.1 LSB之間，輸入頻率從直流到Nyquist頻率的SNDR都能大於60 dB，在350 MHz取樣頻率而訊號頻率接近Nyquist頻率且使用單一電源時，功率消耗為36.2 mW。這個數位類比轉換器採用TSMC 1P5M 0.25 μm CMOS製程來實現，整個晶片在核心部分的面積只有0.09 mm2，佈局後模擬在350 MHz取樣頻率而訊號頻率為170 MHz的SNDR為55.96 dB。

    　　A 10-bit 350-MSample/s Nyquist CMOS digital-to-analog converter is proposed in this thesis. Segmented current steering architecture that comprises 6MSB’s unary cells and 4LSB’s binary-weighted cells is applied in this design. Proper area of current source transistor is chosen to overcome mismatch error due to process variation. Cascoded switch structure is adopted in the current cell which improves the performance of the segmented DAC, such as INL and SNDR. In addition, a high speed and high crossing point switch driver is designed to minimize glitch error.
    　　The simulation results show that INL is better than ±0.2 LSB and DNL is between ±0.1 LSB. SNDR better than 60 dB is simulated in the interval from dc to the Nyquist frequency. The power consumption of this DAC with a single 2.5 V supply is 36 mW for a near-Nyquist fundamental signal at a 350 MHz update rate. The SNDR of post-simulation for a 170 MHz signal at a 350 MHz update rate is 55.96 dB and the power of the post-simulation is 43.8 mW. The DAC is fabricated using TSMC standard 0.25μm 1P5M CMOS process. The chip has small active area of 0.09 mm2.

    CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Organization of Thesis 2 CHAPTER 2 FUNDAMENTALS OF DIGITAL-TO-ANALOG CONVERTER 4 2.1 Introduction of Digital-to-Analog Converter 4 2.2 Ideal DAC 5 2.3 DAC Performance Metrics 7 2.3.1 Intrinsic Parameters 7 2.3.2 Dynamic Parameters 10 2.3.3 Transmission Parameters 12 2.4 Review of DAC Architecture 14 2.4.1 Decoder-Based Architectures 14 2.4.2 Binary-Weighted Architectures 16 2.4.3 Thermometer-Coded Architecture 20 2.4.4 Hybrid Architecture 23 2.5 Summary 24 CHAPTER 3 IMPLEMENTATION OF THE PROPOSED DIGITAL-TO-AANLOG CONVERTER 25 3.1 Introduction 25 3.2 DAC Architecture 26 3.3 The Current Cell 28 3.3.1 Random Errors 29 3.3.2 Systematic Errors 34 3.3.3 Finite Output Impedance of The Current Cell 37 3.3.4 Voltage Fluctuation 42 3.3.5 Control Signals Feedthrough 45 3.3.6 Circuit Design of This DAC’s Current Cell 46 3.4 High Speed Latch 53 3.5 Digital circuits 56 3.6 Layout 59 3.7 Summary 62 CHAPTER 4 SIMULATIONS AND MEASUREMENTS 63 4.1 Introduction 63 4.2 Simulation results 63 4.3 Measurement Setup 64 CHAPTER 5 CONCLUSIONS AND FURURE WORK 69 5.1 Conclusions 69 5.2 Future Work 70 REFERENCES 71

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